int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
{
static bool first = true;
if (first) {
unsigned long sz = 0x10;
unsigned int i, ncores = scu_get_core_count(RK30_SCU_BASE);
for (i = 1; i < ncores; i++)
pmu_set_power_domain(PD_A9_0 + i, false);
#if defined(CONFIG_ARCH_RK319X)
memcpy(RK319X_BOOT_BASE, rk30_sram_secondary_startup, sz);
#else
memcpy(RK30_IMEM_NONCACHED, rk30_sram_secondary_startup, sz);
#endif
isb();
dsb();
first = false;
}
pmu_set_power_domain(PD_A9_0 + cpu, true);
return 0;
}
static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *node;
unsigned int i;
node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
if (!node) {
pr_err("%s: missing scu\n", __func__);
return;
}
scu_base_addr = of_iomap(node, 0);
if (!scu_base_addr) {
pr_err("%s: could not map scu registers\n", __func__);
return;
}
node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
if (!node) {
pr_err("%s: could not find sram dt node\n", __func__);
return;
}
if (rockchip_smp_prepare_sram(node))
return;
node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
if (!node) {
pr_err("%s: could not find pmu dt node\n", __func__);
return;
}
pmu_base_addr = of_iomap(node, 0);
if (!pmu_base_addr) {
pr_err("%s: could not map pmu registers\n", __func__);
return;
}
/* enable the SCU power domain */
pmu_set_power_domain(PMU_PWRDN_SCU, true);
/*
* While the number of cpus is gathered from dt, also get the number
* of cores from the scu to verify this value when booting the cores.
*/
ncores = scu_get_core_count(scu_base_addr);
scu_enable(scu_base_addr);
/* Make sure that all cores except the first are really off */
for (i = 1; i < ncores; i++)
pmu_set_power_domain(0 + i, false);
}
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
{
static bool first = true;
if (first) {
unsigned long sz = 0x10;
pmu_set_power_domain(PD_A9_1, false);
memcpy(RK30_IMEM_BASE, rk30_sram_secondary_startup, sz);
flush_icache_range((unsigned long)RK30_IMEM_BASE, (unsigned long)RK30_IMEM_BASE + sz);
outer_clean_range(0, sz);
first = false;
}
dsb_sev();
pmu_set_power_domain(PD_A9_1, true);
return 0;
}
static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
struct task_struct *idle)
{
if (!sram_base_addr || !pmu_base_addr) {
pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
return -ENXIO;
}
if (cpu >= ncores) {
pr_err("%s: cpu %d outside maximum number of cpus %d\n",
__func__, cpu, ncores);
return -ENXIO;
}
/* start the core */
pmu_set_power_domain(0 + cpu, true);
return 0;
}
