static int lsmbus_write_byte(device_t dev, u8 address, u8 val) { unsigned int device; struct resource *res; device = dev->path.i2c.device; res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); pnp_write_index(res->base+HWM_INDEX, 0, device); /* Why 0? */ /* We only write it one byte one time. */ pnp_write_index(res->base+SB_INDEX, address, val); return 0; }
static void init_ec(u16 base) { u8 value; /* Read out current value of FAN_CTL (0x14). */ value = pnp_read_index(base, 0x14); printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\n", base + 0x14, value); /* Set FAN_CTL (0x14) polarity to high, activate fans 1, 2 and 3. */ pnp_write_index(base, 0x14, value | 0x87); printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n", base + 0x14, value | 0x87); }
static int lsmbus_read_byte(device_t dev, u8 address) { unsigned int device; struct resource *res; int result; device = dev->path.i2c.device; res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); pnp_write_index(res->base + HWM_INDEX, 0, device); /* Why 0? */ /* We only read it one byte one time. */ result = pnp_read_index(res->base + SB_INDEX, address); return result; }
static void init_hwm(u16 base) { int i; u8 reg, value; /* reg mask data */ u8 hwm_reg_values[] = { 0x40, 0xff, 0x81, /* Start HWM. */ 0x48, 0x7f, 0x2a, /* Set SMBus base to 0x2a (0x54 >> 1). */ }; for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { reg = hwm_reg_values[i]; value = pnp_read_index(base, reg); value &= 0xff & (~(hwm_reg_values[i + 1])); value |= 0xff & hwm_reg_values[i + 2]; printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, " "value = 0x%02x\n", base, reg, value); pnp_write_index(base, reg, value); } }
void it8728f_hwm_ec_init(struct device *dev) { struct superio_ite_it8728f_config *conf = dev->chip_info; struct resource *res = find_resource(dev, PNP_IDX_IO0); if (!res) { printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); return; } /* I/O port for HWM is at base + 5 */ u16 port = res->base + 5; printk(BIOS_INFO, "ITE IT8728F Super I/O HWM: Initializing Hardware Monitor..\n"); printk(BIOS_DEBUG, "ITE IT8728F Super I/O HWM: Base Address at 0x%x\n", port); pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); /* ITE IT8728F HWM (ordered) programming sequence. */ /* configure fan polarity */ pnp_write_index(port, HWM_CTL_REG, conf->hwm_ctl_register); /* enable fans 1-3 */ pnp_write_index(port, HWM_MAIN_CTL_REG, conf->hwm_main_ctl_register); /* enable termistor temps for temp1-temp3 */ pnp_write_index(port, HWM_ADC_TEMP_CHAN_EN_REG, conf->hwm_adc_temp_chan_en_reg); /* configure which fanX uses which tempY */ pnp_write_index(port, HWM_FAN1_CTL_PWM, conf->hwm_fan1_ctl_pwm); pnp_write_index(port, HWM_FAN2_CTL_PWM, conf->hwm_fan2_ctl_pwm); pnp_write_index(port, HWM_FAN3_CTL_PWM, conf->hwm_fan3_ctl_pwm); pnp_exit_conf_mode(dev); }
/* note: multifunc registers need to be tweaked before here */ void f71869ad_hwm_init(struct device *dev) { const struct superio_fintek_f71869ad_config *conf = dev->chip_info; struct resource *res = find_resource(dev, PNP_IDX_IO0); if (!res) { printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); return; } u16 port = res->base; /* data-sheet default base = 0x229 */ printk(BIOS_INFO, "Fintek F71869AD Super I/O HWM: Initializing Hardware Monitor..\n"); printk(BIOS_DEBUG, "Fintek F71869AD Super I/O HWM: Base Address at 0x%x\n", port); pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); /* Fintek F71869AD HWM (ordered) programming sequence. */ /* SMBus Address p.53 */ pnp_write_index(port, HWM_SMBUS_ADDR, conf->hwm_smbus_address); /* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */ pnp_write_index(port, HWM_SMBUS_CONTROL_REG, conf->hwm_smbus_control_reg); /* Tfan1 = Tnow + (Ta - Tb)*Ct where, */ /* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */ pnp_write_index(port, HWM_FAN1_TEMP_MAP_SEL, conf->hwm_fan1_temp_map_sel); /* set FAN_PROG_SEL = 1 */ pnp_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x8a); /* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL = 1, p.64-65 */ pnp_write_index(port, HWM_FAN_TYPE_SEL_REG, conf->hwm_fan_type_sel_reg); /* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */ pnp_write_index(port, HWM_FAN_MODE_SEL_REG, conf->hwm_fan_mode_sel_reg); /* TFAN1_ADJ_{UP,DOWN}_RATE (Ct = 1/4 up & down) in 0x95 when FAN_PROG_SEL = 1, p.88 */ pnp_write_index(port, HWM_FAN1_TEMP_ADJ_RATE_REG, conf->hwm_fan1_temp_adj_rate_reg); /* set FAN_PROG_SEL = 0 */ pnp_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x0a); /* FAN1 RPM mode p.70 */ pnp_write_index(port, HWM_FAN1_IDX_RPM_MODE, conf->hwm_fan1_idx_rpm_mode); /* FAN1 Segment X Speed Count */ pnp_write_index(port, HWM_FAN1_SEG1_SPEED_COUNT, conf->hwm_fan1_seg1_speed_count); pnp_write_index(port, HWM_FAN1_SEG2_SPEED_COUNT, conf->hwm_fan1_seg2_speed_count); pnp_write_index(port, HWM_FAN1_SEG3_SPEED_COUNT, conf->hwm_fan1_seg3_speed_count); pnp_exit_conf_mode(dev); }