Пример #1
0
void esp_dport_access_int_deinit(void)
{
    portENTER_CRITICAL_ISR(&g_dport_mux);
    dport_core_state[0] = DPORT_CORE_STATE_IDLE;
#ifndef CONFIG_FREERTOS_UNICORE
    dport_core_state[1] = DPORT_CORE_STATE_IDLE;
#endif
    portEXIT_CRITICAL_ISR(&g_dport_mux);
}
Пример #2
0
static uint32_t IRAM_ATTR wifi_int_disable_wrapper(void *wifi_int_mux)
{
    if (xPortInIsrContext()) {
        portENTER_CRITICAL_ISR(wifi_int_mux);
    } else {
        portENTER_CRITICAL(wifi_int_mux);
    }

    return 0;
}
Пример #3
0
/* stall other cpu that this cpu is pending to access dport register start */
void IRAM_ATTR esp_dport_access_stall_other_cpu_start(void)
{
#ifndef CONFIG_FREERTOS_UNICORE
    int cpu_id = xPortGetCoreID();

    if (dport_core_state[0] == DPORT_CORE_STATE_IDLE
            || dport_core_state[1] == DPORT_CORE_STATE_IDLE) {
        return;
    }

#ifdef DPORT_ACCESS_BENCHMARK
    ccount_start[cpu_id] = XTHAL_GET_CCOUNT();
#endif
    BaseType_t intLvl=portENTER_CRITICAL_NESTED();
    oldInterruptLevel[cpu_id]=intLvl;

    if (dport_access_ref[cpu_id] == 0) {
        portENTER_CRITICAL_ISR(&g_dport_mux); 

        dport_access_start[cpu_id] = 0;
        dport_access_end[cpu_id] = 0;

        if (cpu_id == 0) {
            _DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_3_REG, DPORT_CPU_INTR_FROM_CPU_3); //interrupt on cpu1
        } else {
            _DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_2_REG, DPORT_CPU_INTR_FROM_CPU_2); //interrupt on cpu0
        }

        while (!dport_access_start[cpu_id]) {};

        REG_READ(SPI_DATE_REG(3));  //just read a APB register sure that the APB-bus is idle
    }

    dport_access_ref[cpu_id]++;
#endif /* CONFIG_FREERTOS_UNICORE */
}