void vTimer2_ISR_Handler( void )
{
volatile unsigned short usCurrentCount;
static unsigned short usMaxCount = 0;
static unsigned long ulErrorCount = 0UL;
/* This is the highest priority interrupt in the system, so there is no
advantage to re-enabling interrupts here.
We use the timer 1 counter value to measure the clock cycles between
the timer 0 interrupts. First stop the clock. */
CMT.CMSTR1.BIT.STR3 = 0;
portNOP();
portNOP();
usCurrentCount = timerTIMER_3_COUNT_VALUE;
/* Is this the largest count we have measured yet? */
if( usCurrentCount > usMaxCount )
{
if( usCurrentCount > timerEXPECTED_DIFFERENCE_VALUE )
{
usMaxJitter = usCurrentCount - timerEXPECTED_DIFFERENCE_VALUE;
}
else
{
/* This should not happen! */
ulErrorCount++;
}
usMaxCount = usCurrentCount;
}
/* Used to generate the run time stats. */
ulHighFrequencyTickCount++;
/* Clear the timer. */
timerTIMER_3_COUNT_VALUE = 0;
/* Then start the clock again. */
CMT.CMSTR1.BIT.STR3 = 1;
}
unsigned portCHAR __low_level_init( void )
{
unsigned portCHAR resetflag = RESF;
unsigned portBASE_TYPE i = 0;
portDISABLE_INTERRUPTS(); /* disable global interrupts */
PRCMD = 0x00; /* On-chip debug mode */
PCC = 0x00; /* high speed mode fCPU */
VSWC = 0x00;
WDTM2 = 0xF; /* Stop watchdog Timer */
PLLS = 0x03; /* Set PLL stabilisation time */
PLLON = 1; /* activate PLL */
for( i = 0; i <= 2000; i++ ) /* Wait for stabilisation */
{
portNOP();
}
while( LOCK ) /* Wait for PLL frequency stabiliasation */
{
portNOP();
}
SELPLL = 1; /* Set CPU operation to PLL mode */
return pdTRUE;
}
void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
{
( void ) xRegisterDump;
for( ;; )
{
portNOP();
}
}
static void prvTxHandler( void *pvUnused, unsigned portBASE_TYPE uxByteCount )
{
( void ) pvUnused;
( void ) uxByteCount;
/* Nothing to do here. The Xilinx library function takes care of the
transmission. */
portNOP();
}
void task2 (void *pvParameters) {
while(TRUE) {
printf("Task 2\n");
taskYIELD();
for(int i = 0; i < DELAY_LOOP; i++)
portNOP();
}
vTaskDelete(NULL);
}
/**
* This function should do the actual transmission of the packet. The packet is
* contained in the pbuf that is passed to the function. This pbuf
* might be chained.
*
* @param netif the lwip network interface structure for this ethernetif
* @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
* @return ERR_OK if the packet could be sent
* an err_t value if the packet couldn't be sent
*
* @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
* strange results. You might consider waiting for space in the DMA queue
* to become availale since the stack doesn't retry to send a packet
* dropped because of memory failure (except for the TCP timers).
*/
static err_t low_level_output(struct netif *netif, struct pbuf *p)
{
struct pbuf *q;
u32_t l = 0;
unsigned char *pcTxData;
#if ETH_PAD_SIZE
pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
#endif
/* Get a DMA buffer into which we can write the data to send. */
for( int i = 0; i < netifBUFFER_WAIT_ATTEMPTS; i++ ) {
pcTxData = pcGetNextBuffer();
if( pcTxData ) {
break;
} else {
vTaskDelay( netifBUFFER_WAIT_DELAY );
}
}
if (pcTxData == NULL) {
portNOP();
return ERR_BUF;
} else {
for(q = p; q != NULL; q = q->next) {
/* Send the data from the pbuf to the interface, one pbuf at a
time. The size of the data in each pbuf is kept in the ->len
variable. */
vTaskSuspendAll();
memcpy(&pcTxData[l], (u8_t*)q->payload, q->len);
xTaskResumeAll();
l += q->len;
}
}
ENET_TxPkt( &pcTxData, l );
#if ETH_PAD_SIZE
pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
#endif
LINK_STATS_INC(link.xmit);
return ERR_OK;
}
void vAssertCalled( void )
{
volatile unsigned long ul = 0;
taskENTER_CRITICAL();
{
/* Use the debugger to set ul to a non-zero value in order to step out
of this function to determine why it was called. */
while( ul == 0 )
{
portNOP();
}
}
taskEXIT_CRITICAL();
}
void vAssertCalled( const char * pcFile, unsigned long ulLine )
{
volatile unsigned long ul = 0;
( void ) pcFile;
( void ) ulLine;
taskENTER_CRITICAL();
{
/* Set ul to a non-zero value using the debugger to step out of this
function. */
while( ul == 0 ) {
portNOP();
}
}
taskEXIT_CRITICAL();
}
void vAssertCalled( const char * pcFile, unsigned long ulLine )
{
volatile unsigned long ul = 0;
( void ) pcFile;
( void ) ulLine;
__asm volatile( "di" );
{
/* Set ul to a non-zero value using the debugger to step out of this
function. */
while( ul == 0 )
{
portNOP();
}
}
__asm volatile( "ei" );
}
/*
Deallocates a mailbox. If there are messages still present in the
mailbox when the mailbox is deallocated, it is an indication of a
programming error in lwIP and the developer should be notified.
*/
void sys_mbox_free(sys_mbox_t mbox)
{
if( uxQueueMessagesWaiting( mbox ) )
{
/* Line for breakpoint. Should never break here! */
portNOP();
#if SYS_STATS
lwip_stats.sys.mbox.err++;
#endif /* SYS_STATS */
// TODO notify the user of failure.
}
vQueueDelete( mbox );
#if SYS_STATS
--lwip_stats.sys.mbox.used;
#endif /* SYS_STATS */
}
unsigned char __low_level_init(void)
{
unsigned char resetflag = RESF;
unsigned char psval = 0;
unsigned portBASE_TYPE i = 0;
/* Setup provided by NEC. */
portDISABLE_INTERRUPTS(); /* disable global interrupts */
PRCMD = 0x00; /* On-chip debug mode */
OCDM = 0x00;
VSWC = 0x00; /* set system wait control register */
WDTM2 = 0x00; /* WDT2 setting */
PLLON = 0; /* PLL stop mode */
psval = 0x0A | 0x00;
PRCMD = psval; /* set Command Register */
CKC = psval; /* set Clock Control Register */
PLLS = 0x03;
psval = 0x80; /* Set fXX and fCPU */
PRCMD = psval;
PCC = psval;
PLLON = 1; /* activate PLL */
for( i = 0; i <= 2000; i++ ) /* Wait for stabilisation */
{
portNOP();
}
while( LOCK ) /* Wait for PLL frequency stabiliasation */
{
;
}
SELPLL = 1; /* Set PLL mode active */
RSTOP = 0; /* Set fR (enable) */
BGCE0 = 0; /* Set fBRG(disable) */
psval = 0x00; /* Stand-by setting */
PRCMD = psval; /* set Command Register */
PSC = psval; /* set Power Save Control Register */
return pdTRUE;
}
signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait )
{
signed portBASE_TYPE xReturn;
/* If the queue is already empty we may have to block. A critical section
is required to prevent an interrupt adding something to the queue
between the check to see if the queue is empty and blocking on the queue. */
portDISABLE_INTERRUPTS();
{
if( prvIsQueueEmpty( pxQueue ) )
{
/* There are no messages in the queue, do we want to block or just
leave with nothing? */
if( xTicksToWait > ( portTickType ) 0 )
{
/* As this is a co-routine we cannot block directly, but return
indicating that we need to block. */
vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
portENABLE_INTERRUPTS();
return errQUEUE_BLOCKED;
}
else
{
portENABLE_INTERRUPTS();
return errQUEUE_FULL;
}
}
}
portENABLE_INTERRUPTS();
portNOP();
portDISABLE_INTERRUPTS();
{
if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )
{
/* Data is available from the queue. */
pxQueue->pcReadFrom += pxQueue->uxItemSize;
if( pxQueue->pcReadFrom >= pxQueue->pcTail )
{
pxQueue->pcReadFrom = pxQueue->pcHead;
}
--( pxQueue->uxMessagesWaiting );
memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
xReturn = pdPASS;
/* Were any co-routines waiting for space to become available? */
if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) )
{
/* In this instance the co-routine could be placed directly
into the ready list as we are within a critical section.
Instead the same pending ready list mechansim is used as if
the event were caused from within an interrupt. */
if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
{
xReturn = errQUEUE_YIELD;
}
}
}
else
{
xReturn = pdFAIL;
}
}
portENABLE_INTERRUPTS();
return xReturn;
}
signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait )
{
signed portBASE_TYPE xReturn;
/* If the queue is already full we may have to block. A critical section
is required to prevent an interrupt removing something from the queue
between the check to see if the queue is full and blocking on the queue. */
portDISABLE_INTERRUPTS();
{
if( prvIsQueueFull( pxQueue ) )
{
/* The queue is full - do we want to block or just leave without
posting? */
if( xTicksToWait > ( portTickType ) 0 )
{
/* As this is called from a coroutine we cannot block directly, but
return indicating that we need to block. */
vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
portENABLE_INTERRUPTS();
return errQUEUE_BLOCKED;
}
else
{
portENABLE_INTERRUPTS();
return errQUEUE_FULL;
}
}
}
portENABLE_INTERRUPTS();
portNOP();
portDISABLE_INTERRUPTS();
{
if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
{
/* There is room in the queue, copy the data into the queue. */
prvCopyQueueData( pxQueue, pvItemToQueue );
xReturn = pdPASS;
/* Were any co-routines waiting for data to become available? */
if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) )
{
/* In this instance the co-routine could be placed directly
into the ready list as we are within a critical section.
Instead the same pending ready list mechansim is used as if
the event were caused from within an interrupt. */
if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
/* The co-routine waiting has a higher priority so record
that a yield might be appropriate. */
xReturn = errQUEUE_YIELD;
}
}
}
else
{
xReturn = errQUEUE_FULL;
}
}
portENABLE_INTERRUPTS();
return xReturn;
}
void vPortExceptionHandler( void *pvExceptionID )
{
extern void *pxCurrentTCB;
/* Fill an xPortRegisterDump structure with the MicroBlaze context as it
was immediately before the exception occurrence. */
/* First fill in the name and handle of the task that was in the Running
state when the exception occurred. */
xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
configASSERT( pulStackPointerOnFunctionEntry );
/* Obtain the values of registers that were stacked prior to this function
being called, and may have changed since they were stacked. */
xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
/* Obtain the value of all other registers. */
xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
xRegisterDump.ulR20 = mfgpr( R20 );
xRegisterDump.ulR21 = mfgpr( R21 );
xRegisterDump.ulR22 = mfgpr( R22 );
xRegisterDump.ulR23 = mfgpr( R23 );
xRegisterDump.ulR24 = mfgpr( R24 );
xRegisterDump.ulR25 = mfgpr( R25 );
xRegisterDump.ulR26 = mfgpr( R26 );
xRegisterDump.ulR27 = mfgpr( R27 );
xRegisterDump.ulR28 = mfgpr( R28 );
xRegisterDump.ulR29 = mfgpr( R29 );
xRegisterDump.ulR30 = mfgpr( R30 );
xRegisterDump.ulR31 = mfgpr( R31 );
xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
xRegisterDump.ulEAR = mfear();
xRegisterDump.ulESR = mfesr();
xRegisterDump.ulEDR = mfedr();
/* Move the saved program counter back to the instruction that was executed
when the exception occurred. This is only valid for certain types of
exception. */
xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
{
xRegisterDump.ulFSR = mffsr();
}
#else
{
xRegisterDump.ulFSR = 0UL;
}
#endif
/* Also fill in a string that describes what type of exception this is.
The string uses the same ID names as defined in the MicroBlaze standard
library exception header files. */
switch( ( uint32_t ) pvExceptionID )
{
case XEXC_ID_FSL :
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
break;
case XEXC_ID_UNALIGNED_ACCESS :
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
break;
case XEXC_ID_ILLEGAL_OPCODE :
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
break;
case XEXC_ID_M_AXI_I_EXCEPTION :
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
break;
case XEXC_ID_M_AXI_D_EXCEPTION :
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
break;
case XEXC_ID_DIV_BY_ZERO :
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
break;
case XEXC_ID_STACK_VIOLATION :
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
break;
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
case XEXC_ID_FPU :
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
break;
#endif /* XPAR_MICROBLAZE_USE_FPU */
}
/* vApplicationExceptionRegisterDump() is a callback function that the
application can optionally define to receive the populated xPortRegisterDump
structure. If the application chooses not to define a version of
vApplicationExceptionRegisterDump() then the weekly defined default
implementation within this file will be called instead. */
vApplicationExceptionRegisterDump( &xRegisterDump );
/* Must not attempt to leave this function! */
for( ;; )
{
portNOP();
}
}
int __low_level_init(void)
{
unsigned portCHAR ucResetFlag = RESF;
portDISABLE_INTERRUPTS();
/* Clock Configuration:
In this port, to use the internal high speed clock source of the microcontroller
define the configCLOCK_SOURCE as 1 in FreeRTOSConfig.h. To use an external
clock define configCLOCK_SOURCE as 0. */
#if configCLOCK_SOURCE == 1
{
/* Set XT1 and XT2 in Input Port Mode
Set X1 and X2 in Input Port Mode
High speed oscillator frequency 2MHz <= fMX <= 10MHz */
CMC = 0x00;
/* X1 external oszillation stopped. */
MSTOP = 1;
/* Enable internal high speed oszillation. */
HIOSTOP = 0;
MCM0 = 0;
/* Stop internal subsystem clock. */
XTSTOP = 1;
/* Set clock speed. */
CSS = 0;
CKC &= (unsigned portCHAR)~0x07;
CKC |= 0x00;
}
#else
{
/* XT1 and XT2 pin in input port mode
X1 and X2 pin in crystal resonator mode
High speed oszillation frequency 10MHz < fMX <= 20MHz */
CMC = 0x41;
/* Set oscillation stabilization time. */
OSTS = 0x07;
/* Set speed mode: fMX > 10MHz for Flash memory high speed operation. */
OSMC = 0x01;
/* Start up X1 oscillator operation
Internal high-speed oscillator operating. */
MSTOP = 0;
/* Check oscillation stabilization time status. */
while(OSTC < 0x07)
{
/* Wait until X1 clock stabilization time. */
portNOP();
}
/* Switch CPU clock to X1 oscillator. */
MCM0 = 1;
while(MCS != 1)
{
/* Wait until CPU and peripherals operate with fX1 clock. */
portNOP();
}
/* Stop the internal high-speed oscillator operation. */
HIOSTOP = 1;
/* Stop the XT1 oscillator operation. */
XTSTOP = 1;
/* Operating frequency f = fx
Change clock generator setting, if necessary. */
CKC &= 0xF8;
/* From here onwards the X1 oscillator is supplied to the CPU. */
}
#endif
/* LED port initialization - set port register. */
P7 = 0x80;
/* Set port mode register. */
PM7 = 0x3F;
/* Switch pin initialization - enable pull-up resistor. */
PU12_bit.no0 = 1;
/* INTP0 is used by the button on the target board. */
/* INTP0 disable. */
PMK0 = 1;
/* INTP0 IF clear. */
PIF0 = 0;
EGN0_bit.no0 = 1;
/* INTP0 priority low. */
PPR10 = 0;
PPR00 = 1;
/* Enable ext. INTP0 interrupt */
PMK0 = 0;
return pdTRUE;
}
