static int att20c490_probe(void)
{
unsigned char oldcomm, notcomm, oldpel, v;
int flag = 0;
_ramdac_dactocomm();
oldcomm = port_in(PEL_MSK);
_ramdac_dactopel();
oldpel = port_in(PEL_MSK);
notcomm = ~oldcomm;
port_out_r(PEL_MSK, notcomm);
_ramdac_dactocomm();
v = port_in(PEL_MSK);
if (v != notcomm) {
if ((_ramdac_setcomm(0xe0) & 0xe0) == 0xe0) {
if ((_ramdac_setcomm(0x60) & 0xe0) == 0) {
if ((_ramdac_setcomm(2) & 2) > 0)
flag = 1; /* 20c490 */
else
flag = 1; /* 20c493 */
} else {
_ramdac_setcomm(oldcomm);
if (port_in(PEL_MSK) == notcomm)
if (_ramdac_setcomm(0xFF) == 0xFF)
flag = 1; /* 20c491/20c492 */
}
}
}
_ramdac_dactocomm();
port_out_r(PEL_MSK, oldcomm);
_ramdac_dactopel();
port_out_r(PEL_MSK, oldpel);
return flag;
}
static void ark_setregs(const unsigned char regs[], int mode)
{
ark_unlock();
/* Write extended registers. */
__svgalib_outCR(0x46, __svgalib_inCR(0x46) | 0x20); /* Disable Clock Select Latch. */
__svgalib_outSR(0x10, regs[ARK_SR10]);
__svgalib_outSR(0x11, regs[ARK_SR11]);
__svgalib_outSR(0x12, regs[ARK_SR12]);
__svgalib_outSR(0x13, regs[ARK_SR13]);
__svgalib_outSR(0x14, regs[ARK_SR14]);
__svgalib_outSR(0x15, regs[ARK_SR15]);
__svgalib_outSR(0x16, regs[ARK_SR16]);
__svgalib_outSR(0x18, regs[ARK_SR18]);
__svgalib_outSR(0x1C, regs[ARK_SR1C]);
__svgalib_outSR(0x1D, regs[ARK_SR1D]);
__svgalib_outCR(0x40, regs[ARK_CR40]);
__svgalib_outCR(0x41, regs[ARK_CR41]);
__svgalib_outCR(0x42, regs[ARK_CR42]);
__svgalib_outCR(0x44, regs[ARK_CR44]);
port_in(0x3C8);
port_out_r(0x3C6, regs[ARK_PELMASK]);
dac_used->restoreState(regs + ARK_DAC_OFFSET);
__svgalib_outCR(0x46, regs[ARK_CR46]);
}
unsigned char _ramdac_setcomm(unsigned char data)
{
_ramdac_dactocomm();
port_out_r(PEL_MSK, data);
_ramdac_dactocomm();
return port_in(PEL_MSK);
}
static void GENDAC_savestate(unsigned char *regs)
{
unsigned char tmp;
tmp = __svgalib_inSR(0x1c);
__svgalib_outSR(0x1c, tmp | 0x80);
regs[SDAC_COMMAND] = port_in(0x3c6);
regs[SDAC_PLL_WRITEINDEX] = port_in(0x3c8); /* PLL write index */
regs[SDAC_PLL_READINDEX] = port_in(0x3c7); /* PLL read index */
port_out_r(0x3c7, 2); /* index to f2 reg */
regs[SDAC_PLL_M] = port_in(0x3c9); /* f2 PLL M divider */
regs[SDAC_PLL_N1_N2] = port_in(0x3c9); /* f2 PLL N1/N2 divider */
port_out_r(0x3c7, 0x0e); /* index to PLL control */
regs[SDAC_PLL_CONTROL] = port_in(0x3c9); /* PLL control */
__svgalib_outSR(0x1c, tmp & ~0x80);
}
static int set_lut(int index, int red, int green, int blue)
{
if (__svgalib_novga) return 1;
/* prevents lockups */
if ((__svgalib_chipset == MACH64)) {
port_out_r(0x02ec+0x5c00,index);
port_out_r(0x02ec+0x5c01,red);
port_out_r(0x02ec+0x5c01,green);
port_out_r(0x02ec+0x5c01,blue);
return 0;
}
__svgalib_outpal(index,red,green,blue);
return 0;
}
static void GENDAC_restorestate(const unsigned char *regs)
{
unsigned char tmp;
tmp = __svgalib_inseq(0x1c);
__svgalib_outseq(0x1c, tmp | 0x80);
port_out_r(0x3c6, regs[SDAC_COMMAND]);
port_out_r(0x3c8, 2); /* index to f2 reg */
port_out_r(0x3c9, regs[SDAC_PLL_M]); /* f2 PLL M divider */
port_out_r(0x3c9, regs[SDAC_PLL_N1_N2]); /* f2 PLL N1/N2 divider */
port_out_r(0x3c8, 0x0e); /* index to PLL control */
port_out_r(0x3c9, regs[SDAC_PLL_CONTROL]); /* PLL control */
port_out_r(0x3c8, regs[SDAC_PLL_WRITEINDEX]); /* PLL write index */
port_out_r(0x3c7, regs[SDAC_PLL_READINDEX]); /* PLL read index */
__svgalib_outseq(0x1c, tmp);
}
static int get_lut(int index, int *red, int *green, int *blue)
{
if (__svgalib_novga) return 0;
/* prevents lockups on mach64 */
if ((__svgalib_chipset == MACH64)) {
port_out_r(0x02ec+0x5c00,index);
*red=port_in(0x02ec+0x5c01);
*green=port_in(0x02ec+0x5c01);
*blue=port_in(0x02ec+0x5c01);
return 0;
}
__svgalib_inpal(index,red,green,blue);
return 0;
}
static void sis_setpage(int page)
{
port_out_r(0x3cb+__svgalib_io_reloc,page);
port_out_r(0x3cd+__svgalib_io_reloc,page);
}
