int pci_write( int bus, int dev, int func, int reg, DWORD v, int size )
{
WORD base;
struct PCI_CONF conf;
conf.data = 0;
conf.bits.enable = TRUE;
conf.bits.bus = bus;
conf.bits.dev = dev;
conf.bits.func = func;
conf.bits.reg = reg & 0xFC;
port_outd( 0xCF8, conf.data );
base = 0xCFC + (reg & 0x03);
switch( size )
{
case SIZE_BYTE:
port_outb( base, (BYTE)v );
break;
case SIZE_WORD:
port_outw( base, (WORD)v );
break;
case SIZE_DWORD:
port_outd( base, v );
break;
}
return SUCCESS;
}
int int17(void)
{
int timeout, val8;
ioport_t addr;
CARRY;
if (_DX >= NUM_LPTS)
return 1;
addr = READ_WORD(BIOS_ADDRESS_LPT1 + _DX * 2);
if (addr == 0)
return 1;
timeout = READ_BYTE(BIOS_LPT1_TIMEOUT + _DX) << 8;
reset_idle(2);
switch(_AH)
{
case 0:
port_outb(addr, _AL);
val8 = port_inb(addr + 2);
port_outb(addr + 2, val8 | 0x01); // send strobe
port_outb(addr + 2, val8 & ~0x01);
while (((val8 = port_inb(addr + 1)) & LPT_STAT_NOT_ACK) && timeout)
timeout--;
break;
case 1:
val8 = port_inb(addr + 2);
port_outb(addr + 2, val8 & ~0x04); // send init
port_outb(addr + 2, val8 | 0x04);
val8 = port_inb(addr + 1);
break;
case 2:
val8 = port_inb(addr + 1);
break;
default:
return 1;
}
_AH = val8 ^ (LPT_STAT_NOT_ACK | LPT_STAT_NOIOERR);
if (!timeout) _AH |= LPT_STAT_TIMEOUT;
NOCARRY;
return 1;
}
