void post_bootmode_init(void)
{
int bootmode = post_bootmode_get(0);
int newword;
if (post_hotkeys_pressed() && !(bootmode & POST_POWERTEST)) {
newword = BOOTMODE_MAGIC | POST_SLOWTEST;
} else if (bootmode == 0) {
newword = BOOTMODE_MAGIC | POST_POWERON;
} else if (bootmode == POST_POWERON || bootmode == POST_SLOWTEST) {
newword = BOOTMODE_MAGIC | POST_NORMAL;
} else {
/* Use old value */
newword = post_word_load() & ~POST_COLDBOOT;
}
if (bootmode == 0) {
/* We are booting after power-on */
newword |= POST_COLDBOOT;
}
post_word_store(newword);
/* Reset activity record */
gd->post_log_word = 0;
}
/* The mapping used here has to be the same as in setup_ext_logbuff ()
in linux/kernel/printk */
void logbuff_init_ptrs (void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned long *ext_tag;
unsigned long post_word;
char *s;
log_buf = (unsigned char *)(gd->bd->bi_memsize-LOGBUFF_LEN);
ext_tag = (unsigned long *)(log_buf)-4;
ext_log_start = (unsigned long *)(log_buf)-3;
ext_log_size = (unsigned long *)(log_buf)-2;
ext_logged_chars = (unsigned long *)(log_buf)-1;
post_word = post_word_load();
#ifdef CONFIG_POST
/* The post routines have setup the word so we can simply test it */
if (post_word_load () & POST_COLDBOOT) {
logged_chars = log_size = log_start = 0;
*ext_tag = LOGBUFF_MAGIC;
}
#else
/* No post routines, so we do our own checking */
if (post_word != LOGBUFF_MAGIC) {
logged_chars = log_size = log_start = 0;
post_word_store (LOGBUFF_MAGIC);
*ext_tag = LOGBUFF_MAGIC;
}
#endif
/* Initialize default loglevel if present */
if ((s = getenv ("loglevel")) != NULL)
console_loglevel = (int)simple_strtoul (s, NULL, 10);
gd->post_log_word |= LOGBUFF_INITIALIZED;
}
int interrupt_init_cpu(unsigned long *decrementer_count)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_pic_t *pic = &immr->im_pic;
#ifdef CONFIG_POST
/*
* The POST word is stored in the PIC's TFRR register which gets
* cleared when the PIC is reset. Save it off so we can restore it
* later.
*/
ulong post_word = post_word_load();
#endif
pic->gcr = MPC86xx_PICGCR_RST;
while (pic->gcr & MPC86xx_PICGCR_RST)
;
pic->gcr = MPC86xx_PICGCR_MODE;
*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %ld\n",
(get_tbclk() / 1000000),
*decrementer_count);
#ifdef CONFIG_INTERRUPTS
pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1);
pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2);
pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3);
#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */
debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8);
#endif
#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */
debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9);
#endif
pic->ctpr = 0; /* 40080 clear current task priority register */
#endif
#ifdef CONFIG_POST
post_word_store(post_word);
#endif
return 0;
}
void logbuff_init_ptrs (void)
{
unsigned long tag, post_word;
char *s;
#ifdef CONFIG_ALT_LB_ADDR
log = (logbuff_t *)CONFIG_ALT_LH_ADDR;
lbuf = (char *)CONFIG_ALT_LB_ADDR;
#else
log = (logbuff_t *)(logbuffer_base ()) - 1;
lbuf = (char *)log->buf;
#endif
/* Set up log version */
if ((s = getenv ("logversion")) != NULL)
log_version = (int)simple_strtoul (s, NULL, 10);
if (log_version == 2)
tag = log->v2.tag;
else
tag = log->v1.tag;
post_word = post_word_load();
#ifdef CONFIG_POST
/* The post routines have setup the word so we can simply test it */
if (tag != LOGBUFF_MAGIC || (post_word & POST_COLDBOOT)) {
logbuff_reset ();
}
#else
/* No post routines, so we do our own checking */
if (tag != LOGBUFF_MAGIC || post_word != LOGBUFF_MAGIC) {
logbuff_reset ();
post_word_store (LOGBUFF_MAGIC);
}
#endif
if (log_version == 2 && (long)log->v2.start > (long)log->v2.con)
log->v2.start = log->v2.con;
/* Initialize default loglevel if present */
if ((s = getenv ("loglevel")) != NULL)
console_loglevel = (int)simple_strtoul (s, NULL, 10);
gd->flags |= GD_FLG_LOGINIT;
}
int misc_init_r(void)
{
u32 pbcr;
int size_val = 0;
u32 post_magic;
u32 post_val;
post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC);
post_val = in_be32((void *)CONFIG_SYS_POST_VAL);
if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) {
/*
* Set special bootline bootparameter to pass this POST boot
* mode to Linux to reset the username/password
*/
setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes");
/*
* Normally don't run POST tests, only when enabled
* via the sw-reset button. So disable further tests
* upon next bootup here.
*/
out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_NOP);
} else {
/*
* Only run POST when initiated via the sw-reset button mechanism
*/
post_word_store(0);
}
/*
* Get current time
*/
start_time = get_timer(0);
/*
* FLASH stuff...
*/
/* Re-do sizing to get full correct info */
/* adjust flash start and offset */
mfebc(PB0CR, pbcr);
switch (gd->bd->bi_flashsize) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
case 32 << 20:
size_val = 5;
break;
case 64 << 20:
size_val = 6;
break;
case 128 << 20:
size_val = 7;
break;
}
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtebc(PB0CR, pbcr);
/*
* Re-check to get correct base address
*/
flash_get_size(gd->bd->bi_flashstart, 0);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
/* Env protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
return 0;
}