void nes_g101_device::write_h(offs_t offset, uint8_t data)
{
LOG_MMC(("g101 write_h, offset: %04x, data: %02x\n", offset, data));
switch (offset & 0x7000)
{
case 0x0000:
if (m_latch)
{
prg8_89(0xfe);
prg8_cd(data & 0x1f);
}
else
{
prg8_89(data & 0x1f);
prg8_cd(0xfe);
}
break;
case 0x1000:
m_latch = BIT(data, 1);
if (m_pcb_ctrl_mirror)
set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
break;
case 0x2000:
prg8_ab(data & 0x1f);
break;
case 0x3000:
chr1_x(offset & 0x07, data & 0x7f, CHRROM);
break;
}
}
void nes_konami_vrc4_device::set_prg()
{
if (m_latch & 0x02)
{
prg8_89(0xfe);
prg8_cd(m_mmc_prg_bank);
}
else
{
prg8_89(m_mmc_prg_bank);
prg8_cd(0xfe);
}
}
void nes_tengen032_device::set_prg()
{
UINT8 prg_mode = m_latch & 0x40;
prg8_89(m_mmc_prg_bank[prg_mode ? 2: 0]);
prg8_ab(m_mmc_prg_bank[prg_mode ? 0: 1]);
prg8_cd(m_mmc_prg_bank[prg_mode ? 1: 2]);
}
void nes_ks7016_device::pcb_reset()
{
prg8_89(0xc);
prg8_ab(0xd);
prg8_cd(0xe);
prg8_ef(0xf);
chr8(0, CHRRAM);
m_reg = 4;
}
void nes_ks7037_device::update_prg()
{
prg8_89(m_reg[6]);
prg8_ab(0xfe);
prg8_cd(m_reg[7]);
prg8_ef(0xff);
set_nt_page(0, CIRAM, m_reg[2] & 1, 1);
set_nt_page(1, CIRAM, m_reg[3] & 1, 1);
set_nt_page(2, CIRAM, m_reg[4] & 1, 1);
set_nt_page(3, CIRAM, m_reg[5] & 1, 1);
}
void nes_benshieng_device::update_banks()
{
prg8_89(m_mmc_prg_bank[0]);
prg8_ab(m_mmc_prg_bank[1]);
prg8_cd(m_mmc_prg_bank[2]);
prg8_ef(m_mmc_prg_bank[3]);
chr2_0(m_mmc_vrom_bank[0], CHRROM);
chr2_2(m_mmc_vrom_bank[1], CHRROM);
chr2_4(m_mmc_vrom_bank[2], CHRROM);
chr2_6(m_mmc_vrom_bank[3], CHRROM);
}
void nes_ks7037_device::pcb_reset()
{
prg8_89(0);
prg8_ab(0x1e);
prg8_cd(0);
prg8_ef(0x1f);
chr8(0, CHRRAM);
memset(m_reg, 0, sizeof(m_reg));
m_latch = 0;
}
void nes_lh10_device::pcb_reset()
{
chr8(0, CHRRAM);
prg8_89(0);
prg8_ab(0);
// 0xc000-0xdfff reads/writes WRAM
prg8_ef(0xff);
memset(m_reg, 0, sizeof(m_reg));
m_latch = 0;
}
void nes_smb3p_device::pcb_reset()
{
m_chr_source = m_vrom_chunks ? CHRROM : CHRRAM;
prg8_89((m_prg_chunks << 1) - 1);
prg8_ab(0);
prg8_cd(0);
prg8_ef((m_prg_chunks << 1) - 1);
chr8(0, m_chr_source);
m_irq_enable = 0;
m_irq_count = 0;
}
void nes_lh53_device::pcb_reset()
{
chr8(0, CHRRAM);
prg8_89(0xc);
prg8_ab(0xd); // last 2K are overlayed by WRAM
prg8_cd(0xe); // first 6K are overlayed by WRAM
prg8_ef(0xf);
m_reg = 0;
m_irq_count = 0;
m_irq_enable = 0;
}
void nes_smb2jb_device::pcb_reset()
{
m_chr_source = m_vrom_chunks ? CHRROM : CHRRAM;
prg8_89(0x08);
prg8_ab(0x09);
prg8_cd(0);
prg8_ef(0x0b);
chr8(0, m_chr_source);
m_irq_enable = 0;
m_irq_count = 0;
}
void nes_pxrom_device::pcb_reset()
{
m_chr_source = m_vrom_chunks ? CHRROM : CHRRAM;
prg8_89(0);
prg8_ab((m_prg_chunks << 1) - 3);
prg8_cd((m_prg_chunks << 1) - 2);
prg8_ef((m_prg_chunks << 1) - 1);
chr8(0, m_chr_source);
m_reg[0] = m_reg[2] = 0;
m_reg[1] = m_reg[3] = 0;
m_latch1 = m_latch2 = 0xfe;
}
void nes_ax5705_device::pcb_reset()
{
m_chr_source = m_vrom_chunks ? CHRROM : CHRRAM;
chr8(0, m_chr_source);
m_mmc_prg_bank[0] = 0;
m_mmc_prg_bank[1] = 1;
prg8_89(m_mmc_prg_bank[0]);
prg8_ab(m_mmc_prg_bank[1]);
prg8_cd(0xfe);
prg8_ef(0xff);
memset(m_mmc_vrom_bank, 0, sizeof(m_mmc_vrom_bank));
}
void nes_h3001_device::write_h(offs_t offset, uint8_t data)
{
LOG_MMC(("h3001 write_h, offset %04x, data: %02x\n", offset, data));
switch (offset & 0x7fff)
{
case 0x0000:
prg8_89(data);
break;
case 0x1001:
set_nt_mirroring(BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
break;
case 0x1003:
m_irq_enable = data & 0x80;
set_irq_line(CLEAR_LINE);
break;
case 0x1004:
m_irq_count = m_irq_count_latch;
set_irq_line(CLEAR_LINE);
break;
case 0x1005:
m_irq_count_latch = (m_irq_count_latch & 0x00ff) | (data << 8);
break;
case 0x1006:
m_irq_count_latch = (m_irq_count_latch & 0xff00) | data;
break;
case 0x2000:
prg8_ab(data);
break;
case 0x3000: case 0x3001: case 0x3002: case 0x3003:
case 0x3004: case 0x3005: case 0x3006: case 0x3007:
chr1_x(offset & 0x07, data, CHRROM);
break;
case 0x4000:
prg8_cd(data);
break;
default:
break;
}
}
void nes_konami_vrc7_device::pcb_reset()
{
m_chr_source = m_vrom_chunks ? CHRROM : CHRRAM;
prg8_89(0);
prg8_ab(0);
prg8_cd(0);
prg8_ef(0xff);
chr8(0, m_chr_source);
m_irq_mode = 0;
m_irq_prescale = 341;
m_irq_enable = 0;
m_irq_enable_latch = 0;
m_irq_count = 0;
m_irq_count_latch = 0;
}
void nes_cne_fsb_device::write_m(offs_t offset, uint8_t data)
{
LOG_MMC(("cne_fsb write_m, offset: %04x, data: %02x\n", offset, data));
if (offset < 0x0800)
{
switch (offset & 0x0007)
{
case 0x0000:
prg8_89(data);
break;
case 0x0001:
prg8_ab(data);
break;
case 0x0002:
prg8_cd(data);
break;
case 0x0003:
prg8_ef(data);
break;
case 0x0004:
chr2_0(data, CHRROM);
break;
case 0x0005:
chr2_2(data, CHRROM);
break;
case 0x0006:
chr2_4(data, CHRROM);
break;
case 0x0007:
chr2_6(data, CHRROM);
break;
}
}
else
m_battery[offset] = data;
}
void nes_hengg_shjy3_device::update_banks()
{
prg8_89(m_mmc_prg_bank[0]);
prg8_ab(m_mmc_prg_bank[1]);
for (int i = 0; i < 8; i++)
{
UINT8 chr_bank = m_mmc_vrom_bank[i] | (m_mmc_extra_bank[i] << 4);
if (m_mmc_vrom_bank[i] == 0xc8)
{
m_chr_mode = 0;
continue;
}
else if (m_mmc_vrom_bank[i] == 0x88)
{
m_chr_mode = 1;
continue;
}
if ((m_mmc_vrom_bank[i] == 4 || m_mmc_vrom_bank[i] == 5) && !m_chr_mode)
chr1_x(i, chr_bank & 1, CHRRAM);
else
chr1_x(i, chr_bank, CHRROM);
}
}
void nes_ks7032_device::prg_update()
{
prg8_89(m_reg[1]);
prg8_ab(m_reg[2]);
prg8_cd(m_reg[3]);
}
void nes_exrom_device::update_prg()
{
int bank0, bank1, bank2, bank3;
switch (m_prg_mode)
{
case 0: // 32k banks
bank3 = m_prg_regs[3] >> 2;
prg32(bank3);
break;
case 1: // 16k banks
bank1 = m_prg_regs[1] >> 1;
bank3 = m_prg_regs[3] >> 1;
if (m_prg_ram_mapped[1])
{
m_ram_hi_banks[0] = ((bank1 << 1) & 0x07);
m_ram_hi_banks[1] = ((bank1 << 1) & 0x07) | 1;
}
else
prg16_89ab(bank1);
prg16_cdef(bank3);
break;
case 2: // 16k-8k banks
bank1 = m_prg_regs[1] >> 1;
bank2 = m_prg_regs[2];
bank3 = m_prg_regs[3];
if (m_prg_ram_mapped[1])
{
m_ram_hi_banks[0] = ((bank1 << 1) & 0x07);
m_ram_hi_banks[1] = ((bank1 << 1) & 0x07) | 1;
}
else
prg16_89ab(bank1);
if (m_prg_ram_mapped[2])
m_ram_hi_banks[2] = (bank2 & 0x07);
else
prg8_cd(bank2);
prg8_ef(bank3);
break;
case 3: // 8k banks
bank0 = m_prg_regs[0];
bank1 = m_prg_regs[1];
bank2 = m_prg_regs[2];
bank3 = m_prg_regs[3];
if (m_prg_ram_mapped[0])
m_ram_hi_banks[0] = (bank0 & 0x07);
else
prg8_89(bank0);
if (m_prg_ram_mapped[1])
m_ram_hi_banks[1] = (bank1 & 0x07);
else
prg8_ab(bank1);
if (m_prg_ram_mapped[2])
m_ram_hi_banks[2] = (bank2 & 0x07);
else
prg8_cd(bank2);
prg8_ef(bank3);
break;
}
}
void nes_ax5705_device::set_prg()
{
prg8_89(m_mmc_prg_bank[0]);
prg8_ab(m_mmc_prg_bank[1]);
}
void nes_exrom_device::update_prg()
{
int bank0, bank1, bank2, bank3;
switch (m_prg_mode)
{
case 0: // 32k banks
bank3 = m_prg_regs[3];
prg32(bank3 >> 2);
break;
case 1: // 16k banks
bank1 = m_prg_regs[1];
bank3 = m_prg_regs[3];
if (!BIT(bank1, 7)) // PRG RAM
{
prgram_bank8_x(0, (bank1 & 0x06));
prgram_bank8_x(1, (bank1 & 0x06) + 1);
}
else
prg16_89ab(bank1 >> 1);
prg16_cdef(bank3);
break;
case 2: // 16k-8k banks
bank1 = m_prg_regs[1];
bank2 = m_prg_regs[2];
bank3 = m_prg_regs[3];
if (!BIT(bank1, 7))
{
prgram_bank8_x(0, (bank1 & 0x06));
prgram_bank8_x(1, (bank1 & 0x06) + 1);
}
else
prg16_89ab((bank1 & 0x7f) >> 1);
if (!BIT(bank2, 7))
prgram_bank8_x(2, bank2 & 0x07);
else
prg8_cd(bank2 & 0x7f);
prg8_ef(bank3);
break;
case 3: // 8k banks
bank0 = m_prg_regs[0];
bank1 = m_prg_regs[1];
bank2 = m_prg_regs[2];
bank3 = m_prg_regs[3];
if (!BIT(bank0, 7))
prgram_bank8_x(0, bank0 & 0x07);
else
prg8_89(bank0 & 0x7f);
if (!BIT(bank1, 7))
prgram_bank8_x(1, bank1 & 0x07);
else
prg8_ab(bank1 & 0x7f);
if (!BIT(bank2, 7))
prgram_bank8_x(2, bank2 & 0x07);
else
prg8_cd(bank2 & 0x7f);
prg8_ef(bank3);
break;
}
}
