static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *SegReg;
SegReg = MCInst_getOperand(MI, Op+1);
SStream_concat0(O, markup("<mem:"));
// If this has a segment register, print it.
if (MCOperand_getReg(SegReg)) {
printOperand(MI, Op+1, O);
SStream_concat0(O, ":");
}
SStream_concat0(O, "(");
printOperand(MI, Op, O);
SStream_concat(O, ")%s", markup(">"));
}
void printOperands(EncoderBase::Operands& opnds) {
unsigned int sz;
if(!dump_x86_inst) return;
for(unsigned int k = 0; k < opnds.count(); k++) {
if(k > 0) {
sz = strlen(tmpBuffer);
sz += snprintf(&tmpBuffer[sz], MAX_DECODED_STRING_LEN-sz, ", ");
}
printOperand(opnds[opnds.count()-1-k]);
}
}
static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
printOperand(MI, OpNo, O);
return;
}
// Branches can take an immediate operand. This is used by the branch
// selection pass to print .+8, an eight byte displacement from the PC.
printAbsBranchOperand(MI, OpNo, O);
}
// ------------------------------------------------------------ Print operands stack
void printAnds( const Stack Ands )
{
Iter si = newIter( Ands );
printf( "\nStack has %d items: bottom<[ ", sizeStack( Ands ) );
while (hasNextIter( si )) {
printOperand( nextIter( si ) );
}
printf( " ]>top\n" );
freeIter( si );
}
static void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O)
{
set_mem_access(MI, true);
//printBranchOperand(MI, OpNo, O);
// On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
// come at the _end_ of the expression.
SStream_concat0(O, "(");
printOperand(MI, OpNo + 1, O);
SStream_concat0(O, ")");
set_mem_access(MI, false);
}
bool AVRAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
const char *ExtraCode, raw_ostream &O) {
// Default asm printer can only deal with some extra codes,
// so try it first.
bool Error = AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
if (Error && ExtraCode && ExtraCode[0]) {
if (ExtraCode[1] != 0)
return true; // Unknown modifier.
if (ExtraCode[0] >= 'A' && ExtraCode[0] <= 'Z') {
const MachineOperand &RegOp = MI->getOperand(OpNum);
assert(RegOp.isReg() && "Operand must be a register when you're"
"using 'A'..'Z' operand extracodes.");
unsigned Reg = RegOp.getReg();
unsigned ByteNumber = ExtraCode[0] - 'A';
unsigned OpFlags = MI->getOperand(OpNum - 1).getImm();
unsigned NumOpRegs = InlineAsm::getNumOperandRegisters(OpFlags);
(void)NumOpRegs;
const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>();
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8;
assert(BytesPerReg <= 2 && "Only 8 and 16 bit regs are supported.");
unsigned RegIdx = ByteNumber / BytesPerReg;
assert(RegIdx < NumOpRegs && "Multibyte index out of range.");
Reg = MI->getOperand(OpNum + RegIdx).getReg();
if (BytesPerReg == 2) {
Reg = TRI.getSubReg(Reg, ByteNumber % BytesPerReg ? AVR::sub_hi
: AVR::sub_lo);
}
O << AVRInstPrinter::getPrettyRegisterName(Reg, MRI);
return false;
}
}
if (Error)
printOperand(MI, OpNum, O);
return false;
}
//TODO: the order of operands
//to make the printout have the same order as assembly in .S
//I reverse the order here
void printDecoderInst(Inst & decInst) {
unsigned int sz;
if(!dump_x86_inst) return;
sz = strlen(tmpBuffer);
sz += snprintf(&tmpBuffer[sz], MAX_DECODED_STRING_LEN-sz, "%s ",
EncoderBase::toStr(decInst.mn));
for(unsigned int k = 0; k < decInst.argc; k++) {
if(k > 0) {
sz = strlen(tmpBuffer);
sz += snprintf(&tmpBuffer[sz], MAX_DECODED_STRING_LEN-sz, ", ");
}
printOperand(decInst.operands[decInst.argc-1-k]);
}
printf("%s\n", tmpBuffer);
}
static void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O)
{
set_mem_access(MI, true);
printS16ImmOperand_Mem(MI, OpNo, O);
SStream_concat0(O, "(");
if (MCOperand_getReg(MCInst_getOperand(MI, OpNo + 1)) == PPC_R0)
SStream_concat0(O, "0");
else
printOperand(MI, OpNo + 1, O);
SStream_concat0(O, ")");
set_mem_access(MI, false);
}
static void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
unsigned short Imm = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Imm);
else
SStream_concat(O, "%u", Imm);
if (MI->csh->detail) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
MI->flat_insn->detail->ppc.op_count++;
}
} else
printOperand(MI, OpNo, O);
}
static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, opNum);
if (MCOperand_isImm(MO)) {
uint8_t imm = (uint8_t)MCOperand_getImm(MO);
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", imm);
else
SStream_concat(O, "%u", imm);
if (MI->csh->detail) {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = imm;
MI->flat_insn.mips.op_count++;
}
} else
printOperand(MI, opNum, O);
}
void AVRInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
unsigned Opcode = MI->getOpcode();
// First handle load and store instructions with postinc or predec
// of the form "ld reg, X+".
// TODO: We should be able to rewrite this using TableGen data.
switch (Opcode) {
case AVR::LDRdPtr:
case AVR::LDRdPtrPi:
case AVR::LDRdPtrPd:
O << "\tld\t";
printOperand(MI, 0, O);
O << ", ";
if (Opcode == AVR::LDRdPtrPd)
O << '-';
printOperand(MI, 1, O);
if (Opcode == AVR::LDRdPtrPi)
O << '+';
break;
case AVR::STPtrRr:
O << "\tst\t";
printOperand(MI, 0, O);
O << ", ";
printOperand(MI, 1, O);
break;
case AVR::STPtrPiRr:
case AVR::STPtrPdRr:
O << "\tst\t";
if (Opcode == AVR::STPtrPdRr)
O << '-';
printOperand(MI, 1, O);
if (Opcode == AVR::STPtrPiRr)
O << '+';
O << ", ";
printOperand(MI, 2, O);
break;
default:
if (!printAliasInstr(MI, O))
printInstruction(MI, O);
printAnnotation(O, Annot);
break;
}
}
static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *SegReg;
int reg;
if (MI->csh->detail) {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
#ifndef CAPSTONE_DIET
get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
#endif
}
SegReg = MCInst_getOperand(MI, Op+1);
reg = MCOperand_getReg(SegReg);
// If this has a segment register, print it.
if (reg) {
_printOperand(MI, Op+1, O);
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg;
}
SStream_concat0(O, ":");
}
SStream_concat0(O, "[");
set_mem_access(MI, true);
printOperand(MI, Op, O);
SStream_concat0(O, "]");
set_mem_access(MI, false);
}
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
printOperand(MI, OpNo, O);
return;
}
int tmp = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4;
if (tmp >= 0) {
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "0x%x", tmp);
else
SStream_concat(O, "%u", tmp);
} else {
if (tmp < -HEX_THRESHOLD)
SStream_concat(O, "-0x%x", -tmp);
else
SStream_concat(O, "-%u", -tmp);
}
}
static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *DispSpec = MCInst_getOperand(MI, Op);
MCOperand *SegReg = MCInst_getOperand(MI, Op+1);
SStream_concat0(O, markup("<mem:"));
// If this has a segment register, print it.
if (MCOperand_getReg(SegReg)) {
printOperand(MI, Op+1, O);
SStream_concat0(O, ":");
}
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
}
if (MCOperand_isImm(DispSpec)) {
int64_t imm = MCOperand_getImm(DispSpec);
if (MI->csh->detail)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
if (imm < 0) {
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm);
} else {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
}
}
SStream_concat0(O, markup(">"));
if (MI->csh->detail)
MI->flat_insn->detail->x86.op_count++;
}
void M680X_printInst(MCInst *MI, SStream *O, void *PrinterInfo)
{
m680x_info *info = (m680x_info *)PrinterInfo;
cs_m680x *m680x = &info->m680x;
cs_detail *detail = MI->flat_insn->detail;
int suppress_operands = 0;
const char *delimiter = getDelimiter(info, m680x);
int i;
if (detail != NULL)
memcpy(&detail->m680x, m680x, sizeof(cs_m680x));
if (info->insn == M680X_INS_INVLD || info->insn == M680X_INS_ILLGL) {
if (m680x->op_count)
SStream_concat(O, "fcb $%02x", m680x->operands[0].imm);
else
SStream_concat(O, "fcb $<unknown>");
return;
}
printInstructionName(MI->csh, O, info->insn);
SStream_concat(O, " ");
if ((m680x->flags & M680X_FIRST_OP_IN_MNEM) != 0)
suppress_operands++;
if ((m680x->flags & M680X_SECOND_OP_IN_MNEM) != 0)
suppress_operands++;
for (i = 0; i < m680x->op_count; ++i) {
if (i >= suppress_operands) {
printOperand(MI, O, info, &m680x->operands[i]);
if ((i + 1) != m680x->op_count)
SStream_concat(O, delimiter);
}
}
}
void AVRInstPrinter::printMemri(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
assert(MI->getOperand(OpNo).isReg() && "Expected a register for the first operand");
const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
// Print the register.
printOperand(MI, OpNo, O);
// Print the {+,-}offset.
if (OffsetOp.isImm()) {
int64_t Offset = OffsetOp.getImm();
if (Offset >= 0)
O << '+';
O << Offset;
} else if (OffsetOp.isExpr()) {
O << *OffsetOp.getExpr();
} else {
llvm_unreachable("unknown type for offset");
}
}
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
int imm;
if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
printOperand(MI, OpNo, O);
return;
}
imm = ((int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)) << 2);
if (!PPC_abs_branch(MI->csh, MCInst_getOpcode(MI))) {
imm = (int)MI->address + imm;
}
SStream_concat(O, "0x%x", imm);
if (MI->csh->detail) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm;
MI->flat_insn->detail->ppc.op_count++;
}
}
static void printUnsignedImm(MCInst *MI, int opNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, opNum);
if (MCOperand_isImm(MO)) {
int64_t imm = MCOperand_getImm(MO);
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", (unsigned short int)imm);
else
SStream_concat(O, "%u", (unsigned short int)imm);
} else {
if (imm <= -HEX_THRESHOLD)
SStream_concat(O, "-0x%x", (short int)-imm);
else
SStream_concat(O, "-%u", (short int)-imm);
}
if (MI->csh->detail) {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = (unsigned short int)imm;
MI->flat_insn.mips.op_count++;
}
} else
printOperand(MI, opNum, O);
}
static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *SegReg;
int reg;
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
}
SegReg = MCInst_getOperand(MI, Op+1);
reg = MCOperand_getReg(SegReg);
// If this has a segment register, print it.
if (reg) {
_printOperand(MI, Op+1, O);
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg;
}
SStream_concat0(O, ":");
}
SStream_concat0(O, "(");
set_mem_access(MI, true);
printOperand(MI, Op, O);
SStream_concat0(O, ")");
set_mem_access(MI, false);
}
/*打印中间代码到屏幕*/
void printCodeToTerminal(struct InterCodes* temp){
switch((temp->code).kind){
case ASSIGN_IR:
printf("%s",printOperand((temp->code).u.assign.right));
printf(" := ");
printf("%s\n",printOperand((temp->code).u.assign.left));
break;
case ADD_IR:
printf("%s",printOperand((temp->code).u.binop.result));
printf(" := ");
printf("%s",printOperand((temp->code).u.binop.op1));
printf(" + ");
printf("%s\n",printOperand((temp->code).u.binop.op2));
break;
case SUB_IR:
printf("%s",printOperand((temp->code).u.binop.result));
printf(" := ");
printf("%s",printOperand((temp->code).u.binop.op1));
printf(" - ");
printf("%s\n",printOperand((temp->code).u.binop.op2));
break;
case MUL_IR:
printf("%s",printOperand((temp->code).u.binop.result));
printf(" := ");
printf("%s",printOperand((temp->code).u.binop.op1));
printf(" * ");
printf("%s\n",printOperand((temp->code).u.binop.op2));
break;
case DIV_IR:
printf("%s",printOperand((temp->code).u.binop.result));
printf(" := ");
printf("%s",printOperand((temp->code).u.binop.op1));
printf(" / ");
printf("%s\n",printOperand((temp->code).u.binop.op2));
break;
case FUNC_IR:
printf("FUNCTION %s :\n",(temp->code).u.name);
break;
case LABEL_IR:
printf("LABEL %s :\n",printOperand((temp->code).u.op));
break;
case GOTO_IR:
printf("GOTO ");
printf("%s\n",printOperand((temp->code).u.op));
break;
case IF_IR:
printf("IF ");
printf("%s",printOperand((temp->code).u.if_type.op1));
printf(" %s ",(temp->code).u.if_type.relop);
printf("%s",printOperand((temp->code).u.if_type.op2));
printf(" GOTO ");
printf("%s\n",printOperand((temp->code).u.if_type.lable));
break;
case RETURN_IR:
printf("RETURN ");
printf("%s\n",printOperand((temp->code).u.op));
break;
case DEC_IR:
printf("DEC ");
printf("%s",printOperand((temp->code).u.array.op));
if((temp->code).u.array.size!=0)
printf(" %d\n",(temp->code).u.array.size);
else
printf("\n");
break;
case ARG_IR:
printf("ARG ");
printf("%s\n",printOperand((temp->code).u.op));
break;
case CALL_IR:
printf("%s",printOperand((temp->code).u.call_fun.returnop));
printf(" := CALL ");
printf("%s\n",(temp->code).u.call_fun.name);
break;
case PARAM_IR:
printf("PARAM ");
printf("%s\n",printOperand((temp->code).u.op));
break;
case READ_IR:
printf("READ ");
printf("%s\n",printOperand((temp->code).u.op));
break;
case WRITE_IR:
printf("WRITE ");
printf("%s\n",printOperand((temp->code).u.op));
break;
default:
printf("InterCodes kind type!!!\n");
break;
}
}
static bool printAlias1(char *Str, MCInst *MI, unsigned OpNo, SStream *OS)
{
SStream_concat(OS, "%s\t", Str);
printOperand(MI, OpNo, OS);
return true;
}
void PPC_printInst(MCInst *MI, SStream *O, void *Info)
{
char *mnem;
// Check for slwi/srwi mnemonics.
if (MCInst_getOpcode(MI) == PPC_RLWINM) {
unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
unsigned char MB = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 4));
bool useSubstituteMnemonic = false;
if (SH <= 31 && MB == 0 && ME == (31-SH)) {
SStream_concat0(O, "slwi\t");
MCInst_setOpcodePub(MI, PPC_INS_SLWI);
useSubstituteMnemonic = true;
}
if (SH <= 31 && MB == (32-SH) && ME == 31) {
SStream_concat0(O, "srwi\t");
MCInst_setOpcodePub(MI, PPC_INS_SRWI);
useSubstituteMnemonic = true;
SH = 32-SH;
}
if (useSubstituteMnemonic) {
printOperand(MI, 0, O);
SStream_concat0(O, ", ");
printOperand(MI, 1, O);
if (SH > HEX_THRESHOLD)
SStream_concat(O, ", 0x%x", (unsigned int)SH);
else
SStream_concat(O, ", %u", (unsigned int)SH);
if (MI->csh->detail) {
cs_ppc *ppc = &MI->flat_insn->detail->ppc;
ppc->operands[ppc->op_count].type = PPC_OP_IMM;
ppc->operands[ppc->op_count].imm = SH;
++ppc->op_count;
}
return;
}
}
if ((MCInst_getOpcode(MI) == PPC_OR || MCInst_getOpcode(MI) == PPC_OR8) &&
MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2))) {
SStream_concat0(O, "mr\t");
MCInst_setOpcodePub(MI, PPC_INS_MR);
printOperand(MI, 0, O);
SStream_concat0(O, ", ");
printOperand(MI, 1, O);
return;
}
if (MCInst_getOpcode(MI) == PPC_RLDICR) {
unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
// rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
if (63-SH == ME) {
SStream_concat0(O, "sldi\t");
MCInst_setOpcodePub(MI, PPC_INS_SLDI);
printOperand(MI, 0, O);
SStream_concat0(O, ", ");
printOperand(MI, 1, O);
if (SH > HEX_THRESHOLD)
SStream_concat(O, ", 0x%x", (unsigned int)SH);
else
SStream_concat(O, ", %u", (unsigned int)SH);
return;
}
}
if ((MCInst_getOpcode(MI) == PPC_gBC)||(MCInst_getOpcode(MI) == PPC_gBCA)||
(MCInst_getOpcode(MI) == PPC_gBCL)||(MCInst_getOpcode(MI) == PPC_gBCLA)) {
int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 2));
bd = SignExtend64(bd, 14);
MCOperand_setImm(MCInst_getOperand(MI, 2),bd);
}
if (isBOCTRBranch(MCInst_getOpcode(MI))) {
if (MCOperand_isImm(MCInst_getOperand(MI,0)))
{
int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0));
bd = SignExtend64(bd, 14);
MCOperand_setImm(MCInst_getOperand(MI, 0),bd);
}
}
if ((MCInst_getOpcode(MI) == PPC_B)||(MCInst_getOpcode(MI) == PPC_BA)||
(MCInst_getOpcode(MI) == PPC_BL)||(MCInst_getOpcode(MI) == PPC_BLA)) {
int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0));
bd = SignExtend64(bd, 24);
MCOperand_setImm(MCInst_getOperand(MI, 0),bd);
}
// consider our own alias instructions first
mnem = printAliasInstrEx(MI, O, Info);
if (!mnem)
mnem = printAliasInstr(MI, O, Info);
if (mnem != NULL) {
if (strlen(mnem) > 0) {
struct ppc_alias alias;
// check to remove the last letter of ('.', '-', '+')
if (mnem[strlen(mnem) - 1] == '-' || mnem[strlen(mnem) - 1] == '+' || mnem[strlen(mnem) - 1] == '.')
mnem[strlen(mnem) - 1] = '\0';
if (PPC_alias_insn(mnem, &alias)) {
MCInst_setOpcodePub(MI, alias.id);
if (MI->csh->detail) {
MI->flat_insn->detail->ppc.bc = (ppc_bc)alias.cc;
}
}
}
cs_mem_free(mnem);
} else
printInstruction(MI, O, NULL);
}
static char *printAliasInstrEx(MCInst *MI, SStream *OS, void *info)
{
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
SStream ss;
const char *opCode;
char *tmp, *AsmMnem, *AsmOps, *c;
int OpIdx, PrintMethodIdx;
int decCtr = false, needComma = false;
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
SStream_Init(&ss);
switch (MCInst_getOpcode(MI)) {
default: return NULL;
case PPC_gBC:
opCode = "b%s";
break;
case PPC_gBCA:
opCode = "b%sa";
break;
case PPC_gBCCTR:
opCode = "b%sctr";
break;
case PPC_gBCCTRL:
opCode = "b%sctrl";
break;
case PPC_gBCL:
opCode = "b%sl";
break;
case PPC_gBCLA:
opCode = "b%sla";
break;
case PPC_gBCLR:
opCode = "b%slr";
break;
case PPC_gBCLRL:
opCode = "b%slrl";
break;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 0) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 1)) {
SStream_concat(&ss, opCode, "dnzf");
decCtr = true;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 2) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 3)) {
SStream_concat(&ss, opCode, "dzf");
decCtr = true;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 4) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 7) &&
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
switch(cr) {
case CREQ:
SStream_concat(&ss, opCode, "ne");
break;
case CRGT:
SStream_concat(&ss, opCode, "le");
break;
case CRLT:
SStream_concat(&ss, opCode, "ge");
break;
case CRUN:
SStream_concat(&ss, opCode, "ns");
break;
}
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6)
SStream_concat0(&ss, "-");
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7)
SStream_concat0(&ss, "+");
decCtr = false;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 8) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 9)) {
SStream_concat(&ss, opCode, "dnzt");
decCtr = true;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 10) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 11)) {
SStream_concat(&ss, opCode, "dzt");
decCtr = true;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 12) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 15) &&
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
switch(cr) {
case CREQ:
SStream_concat(&ss, opCode, "eq");
break;
case CRGT:
SStream_concat(&ss, opCode, "gt");
break;
case CRLT:
SStream_concat(&ss, opCode, "lt");
break;
case CRUN:
SStream_concat(&ss, opCode, "so");
break;
}
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14)
SStream_concat0(&ss, "-");
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15)
SStream_concat0(&ss, "+");
decCtr = false;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 16)) {
SStream_concat(&ss, opCode, "dnz");
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24)
SStream_concat0(&ss, "-");
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 25)
SStream_concat0(&ss, "+");
needComma = false;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 18)) {
SStream_concat(&ss, opCode, "dz");
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 26)
SStream_concat0(&ss, "-");
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 27)
SStream_concat0(&ss, "+");
needComma = false;
}
if (MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) < 16)) {
int cr = getBICR(MCOperand_getReg(MCInst_getOperand(MI, 1)));
if (decCtr) {
needComma = true;
SStream_concat0(&ss, " ");
if (cr > PPC_CR0) {
SStream_concat(&ss, "4*cr%d+", cr - PPC_CR0);
}
cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
switch(cr) {
case CREQ:
SStream_concat0(&ss, "eq");
op_addBC(MI, PPC_BC_EQ);
break;
case CRGT:
SStream_concat0(&ss, "gt");
op_addBC(MI, PPC_BC_GT);
break;
case CRLT:
SStream_concat0(&ss, "lt");
op_addBC(MI, PPC_BC_LT);
break;
case CRUN:
SStream_concat0(&ss, "so");
op_addBC(MI, PPC_BC_SO);
break;
}
cr = getBICR(MCOperand_getReg(MCInst_getOperand(MI, 1)));
if (cr > PPC_CR0) {
if (MI->csh->detail) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_CRX;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].crx.scale = 4;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].crx.reg = PPC_REG_CR0 + cr - PPC_CR0;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].crx.cond = MI->flat_insn->detail->ppc.bc;
MI->flat_insn->detail->ppc.op_count++;
}
}
} else {
if (cr > PPC_CR0) {
needComma = true;
SStream_concat(&ss, " cr%d", cr - PPC_CR0);
op_addReg(MI, PPC_REG_CR0 + cr - PPC_CR0);
}
}
}
if (MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
MCOperand_getImm(MCInst_getOperand(MI, 2)) != 0) {
if (needComma)
SStream_concat0(&ss, ",");
SStream_concat0(&ss, " $\xFF\x03\x01");
}
tmp = cs_strdup(ss.buffer);
AsmMnem = tmp;
for(AsmOps = tmp; *AsmOps; AsmOps++) {
if (*AsmOps == ' ' || *AsmOps == '\t') {
*AsmOps = '\0';
AsmOps++;
break;
}
}
SStream_concat0(OS, AsmMnem);
if (*AsmOps) {
SStream_concat0(OS, "\t");
for (c = AsmOps; *c; c++) {
if (*c == '$') {
c += 1;
if (*c == (char)0xff) {
c += 1;
OpIdx = *c - 1;
c += 1;
PrintMethodIdx = *c - 1;
printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
} else
printOperand(MI, *c - 1, OS);
} else {
SStream_concat(OS, "%c", *c);
}
}
}
return tmp;
}
/*打印中间代码到文件*/
void printCodeToFile(char *filename){
struct InterCodes *temp=list_entry(ir_head.next,struct InterCodes,queue);
FILE *fp=fopen(filename,"w");
while(temp!=list_entry(&ir_head,struct InterCodes,queue)){
switch((temp->code).kind){
case ASSIGN_IR:
fprintf(fp,"%s",printOperand((temp->code).u.assign.right));
fprintf(fp," := ");
fprintf(fp,"%s\n",printOperand((temp->code).u.assign.left));
break;
case ADD_IR:
fprintf(fp,"%s",printOperand((temp->code).u.binop.result));
fprintf(fp," := ");
fprintf(fp,"%s",printOperand((temp->code).u.binop.op1));
fprintf(fp," + ");
fprintf(fp,"%s\n",printOperand((temp->code).u.binop.op2));
break;
case SUB_IR:
fprintf(fp,"%s",printOperand((temp->code).u.binop.result));
fprintf(fp," := ");
fprintf(fp,"%s",printOperand((temp->code).u.binop.op1));
fprintf(fp," - ");
fprintf(fp,"%s\n",printOperand((temp->code).u.binop.op2));
break;
case MUL_IR:
fprintf(fp,"%s",printOperand((temp->code).u.binop.result));
fprintf(fp," := ");
fprintf(fp,"%s",printOperand((temp->code).u.binop.op1));
fprintf(fp," * ");
fprintf(fp,"%s\n",printOperand((temp->code).u.binop.op2));
break;
case DIV_IR:
fprintf(fp,"%s",printOperand((temp->code).u.binop.result));
fprintf(fp," := ");
fprintf(fp,"%s",printOperand((temp->code).u.binop.op1));
fprintf(fp," / ");
fprintf(fp,"%s\n",printOperand((temp->code).u.binop.op2));
break;
case LABEL_IR:
fprintf(fp,"LABEL %s :\n",printOperand((temp->code).u.op));
break;
case FUNC_IR:
fprintf(fp,"FUNCTION %s :\n",(temp->code).u.name);
break;
case GOTO_IR:
fprintf(fp,"GOTO ");
fprintf(fp,"%s\n",printOperand((temp->code).u.op));
break;
case IF_IR:
fprintf(fp,"IF ");
fprintf(fp,"%s",printOperand((temp->code).u.if_type.op1));
fprintf(fp," %s ",(temp->code).u.if_type.relop);
fprintf(fp,"%s",printOperand((temp->code).u.if_type.op2));
fprintf(fp," GOTO ");
fprintf(fp,"%s\n",printOperand((temp->code).u.if_type.lable));
break;
case RETURN_IR:
fprintf(fp,"RETURN ");
fprintf(fp,"%s\n",printOperand((temp->code).u.op));
break;
case DEC_IR:
fprintf(fp,"DEC ");
fprintf(fp,"%s",printOperand((temp->code).u.array.op));
if((temp->code).u.array.size!=0)
fprintf(fp," %d\n",(temp->code).u.array.size);
else
fprintf(fp,"\n");
break;
case ARG_IR:
fprintf(fp,"ARG ");
fprintf(fp,"%s\n",printOperand((temp->code).u.op));
break;
case CALL_IR:
fprintf(fp,"%s",printOperand((temp->code).u.call_fun.returnop));
fprintf(fp," := CALL ");
fprintf(fp,"%s\n",(temp->code).u.call_fun.name);
break;
case PARAM_IR:
fprintf(fp,"PARAM ");
fprintf(fp,"%s\n",printOperand((temp->code).u.op));
break;
case READ_IR:
fprintf(fp,"READ ");
fprintf(fp,"%s\n",printOperand((temp->code).u.op));
break;
case WRITE_IR:
fprintf(fp,"WRITE ");
fprintf(fp,"%s\n",printOperand((temp->code).u.op));
break;
default:
printf("InterCodes kind type!!!\n");
break;
}
temp=list_entry(temp->queue.next,struct InterCodes,queue);
}
}
void PPC_printInst(MCInst *MI, SStream *O, void *Info)
{
// Check for slwi/srwi mnemonics.
if (MCInst_getOpcode(MI) == PPC_RLWINM) {
unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
unsigned char MB = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 4));
bool useSubstituteMnemonic = false;
if (SH <= 31 && MB == 0 && ME == (31-SH)) {
SStream_concat(O, "slwi\t");
useSubstituteMnemonic = true;
}
if (SH <= 31 && MB == (32-SH) && ME == 31) {
SStream_concat(O, "srwi\t");
useSubstituteMnemonic = true;
SH = 32-SH;
}
if (useSubstituteMnemonic) {
printOperand(MI, 0, O);
SStream_concat(O, ", ");
printOperand(MI, 1, O);
if (SH > HEX_THRESHOLD)
SStream_concat(O, ", 0x%x", (unsigned int)SH);
else
SStream_concat(O, ", %u", (unsigned int)SH);
return;
}
}
if ((MCInst_getOpcode(MI) == PPC_OR || MCInst_getOpcode(MI) == PPC_OR8) &&
MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
SStream_concat(O, "mr\t");
printOperand(MI, 0, O);
SStream_concat(O, ", ");
printOperand(MI, 1, O);
return;
}
if (MCInst_getOpcode(MI) == PPC_RLDICR) {
unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
// rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
if (63-SH == ME) {
SStream_concat(O, "sldi\t");
printOperand(MI, 0, O);
SStream_concat(O, ", ");
printOperand(MI, 1, O);
if (SH > HEX_THRESHOLD)
SStream_concat(O, ", 0x%x", (unsigned int)SH);
else
SStream_concat(O, ", %u", (unsigned int)SH);
return;
}
}
printInstruction(MI, O, NULL);
}
static void printPredicateOperand(MCInst *MI, unsigned OpNo,
SStream *O, const char *Modifier)
{
unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
MI->flat_insn->detail->ppc.bc = (ppc_bc)cc_normalize(Code);
if (!strcmp(Modifier, "cc")) {
switch ((ppc_predicate)Code) {
default: // unreachable
case PPC_PRED_LT_MINUS:
case PPC_PRED_LT_PLUS:
case PPC_PRED_LT:
SStream_concat0(O, "lt");
return;
case PPC_PRED_LE_MINUS:
case PPC_PRED_LE_PLUS:
case PPC_PRED_LE:
SStream_concat0(O, "le");
return;
case PPC_PRED_EQ_MINUS:
case PPC_PRED_EQ_PLUS:
case PPC_PRED_EQ:
SStream_concat0(O, "eq");
return;
case PPC_PRED_GE_MINUS:
case PPC_PRED_GE_PLUS:
case PPC_PRED_GE:
SStream_concat0(O, "ge");
return;
case PPC_PRED_GT_MINUS:
case PPC_PRED_GT_PLUS:
case PPC_PRED_GT:
SStream_concat0(O, "gt");
return;
case PPC_PRED_NE_MINUS:
case PPC_PRED_NE_PLUS:
case PPC_PRED_NE:
SStream_concat0(O, "ne");
return;
case PPC_PRED_UN_MINUS:
case PPC_PRED_UN_PLUS:
case PPC_PRED_UN:
SStream_concat0(O, "un");
return;
case PPC_PRED_NU_MINUS:
case PPC_PRED_NU_PLUS:
case PPC_PRED_NU:
SStream_concat0(O, "nu");
return;
case PPC_PRED_BIT_SET:
case PPC_PRED_BIT_UNSET:
// llvm_unreachable("Invalid use of bit predicate code");
SStream_concat0(O, "invalid-predicate");
return;
}
}
if (!strcmp(Modifier, "pm")) {
switch ((ppc_predicate)Code) {
case PPC_PRED_LT:
case PPC_PRED_LE:
case PPC_PRED_EQ:
case PPC_PRED_GE:
case PPC_PRED_GT:
case PPC_PRED_NE:
case PPC_PRED_UN:
case PPC_PRED_NU:
return;
case PPC_PRED_LT_MINUS:
case PPC_PRED_LE_MINUS:
case PPC_PRED_EQ_MINUS:
case PPC_PRED_GE_MINUS:
case PPC_PRED_GT_MINUS:
case PPC_PRED_NE_MINUS:
case PPC_PRED_UN_MINUS:
case PPC_PRED_NU_MINUS:
SStream_concat0(O, "-");
return;
case PPC_PRED_LT_PLUS:
case PPC_PRED_LE_PLUS:
case PPC_PRED_EQ_PLUS:
case PPC_PRED_GE_PLUS:
case PPC_PRED_GT_PLUS:
case PPC_PRED_NE_PLUS:
case PPC_PRED_UN_PLUS:
case PPC_PRED_NU_PLUS:
SStream_concat0(O, "+");
return;
case PPC_PRED_BIT_SET:
case PPC_PRED_BIT_UNSET:
// llvm_unreachable("Invalid use of bit predicate code");
SStream_concat0(O, "invalid-predicate");
return;
default: // unreachable
return;
}
// llvm_unreachable("Invalid predicate code");
}
//assert(StringRef(Modifier) == "reg" &&
// "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
printOperand(MI, OpNo + 1, O);
}
void printInstr(struct Instruction i) {
switch (i.op) {
case NOP:
printf("NOP\n");
break;
case HLT:
printf("HLT\n");
break;
case MOV:
printf("MOV ");
printOperand(i.src);
printf(",");
printOperand(i.dst);
printf("\n");
break;
case LW:
printf("LW ");
printOperand(i.src);
printf(",");
printOperand(i.dst);
printf("\n");
break;
case SW:
printf("SW ");
printOperand(i.src);
printf(",");
printOperand(i.dst);
printf("\n");
break;
case ADD:
printf("ADD ");
printOperand(i.src);
printf(",");
printOperand(i.dst);
printf("\n");
break;
case MUL:
printf("MUL ");
printOperand(i.src);
printf(",");
printOperand(i.dst);
printf("\n");
break;
case SUB:
printf("SUB ");
printOperand(i.src);
printf(",");
printOperand(i.dst);
printf("\n");
break;
case DIV:
printf("DIV ");
printOperand(i.src);
printf(",");
printOperand(i.dst);
printf("\n");
break;
case JMPL:
printf("JMPL ");
printOperand(i.src);
if (i.src.lab)
printf("%s",i.src.lab);
printf("\n");
break;
case JMPE:
printf("JMPE ");
printOperand(i.src);
if (i.src.lab)
printf("%s",i.src.lab);
printf("\n");
break;
case JMP:
printf("JMP ");
printOperand(i.src);
if (i.src.lab)
printf("%s",i.src.lab);
printf("\n");
break;
case LABEL:
printf("LABEL %s",i.src.lab);
printf("\n");
break;
case CMP:
printf("CMP ");
printOperand(i.src);
printf(",");
printOperand(i.dst);
printf("\n");
break;
case PRINT:
printf("PRINT ");
printOperand(i.src);
printf("\n");
break;
case READ:
printf("READ ");
printOperand(i.src);
printf("\n");
break;
case PUSH:
printf("PUSH ");
printOperand(i.src);
printf("\n");
break;
case POP:
printf("POP ");
printOperand(i.src);
printf("\n");
break;
case AND:
printf("AND ");
printOperand(i.src);
printf(",");
printOperand(i.dst);
printf("\n");
break;
case OR:
printf("OR ");
printOperand(i.src);
printf(",");
printOperand(i.dst);
printf("\n");
break;
case XOR:
printf("XOR ");
printOperand(i.src);
printf(",");
printOperand(i.dst);
printf("\n");
break;
case LSH:
printf("LSH ");
printOperand(i.src);
printf(",");
printOperand(i.dst);
printf("\n");
break;
case RSH:
printf("RSH ");
printOperand(i.src);
printf(",");
printOperand(i.dst);
printf("\n");
break;
case CALL:
printf("CALL ");
printOperand(i.src);
if (i.src.lab)
printf("%s",i.src.lab);
printf("\n");
break;
case RET:
printf("RET\n");
break;
default:
printf("Instrucction not printed");
printf("\n");
}
}
