/*****************************************
* Compliant with CIM_33's ATINB_MISCIND_POR_TABLE
* Compliant with CIM_33's MISC_INIT_TBL
*****************************************/
static void rs780_por_misc_index_init(device_t nb_dev)
{
printk_info("enter rs780_por_misc_index_init\n");
/* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL
* Block non-snoop DMA request if PMArbDis is set.
* Set BMSetDis */
set_nbmisc_enable_bits(nb_dev, 0x0B, ~0xFFFF0000, 0x00000180);
set_nbmisc_enable_bits(nb_dev, 0x01, ~0xFFFFFFFF, 0x00000040);
/* NBCFG (NBMISCIND 0x0): NB_CNTL -
* HIDE_NB_AGP_CAP ([0], default=1)HIDE
* HIDE_P2P_AGP_CAP ([1], default=1)HIDE
* HIDE_NB_GART_BAR ([2], default=1)HIDE
* AGPMODE30 ([4], default=0)DISABLE
* AGP30ENCHANCED ([5], default=0)DISABLE
* HIDE_AGP_CAP ([8], default=1)ENABLE */
set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000506); /* set bit 10 for MSI */
//lycheng
//set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000004); /* set bit 10 for MSI */
set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 10, 1 << 10); //added by oldtai
set_nbmisc_enable_bits(nb_dev, 0x01, 1 << 8, 1 << 8); //added by oldtai
/* NBMISCIND:0x6A[16]= 1 SB link can get a full swing
* set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000);
* NBMISCIND:0x6A[17]=1 Set CMGOOD_OVERRIDE. */
set_nbmisc_enable_bits(nb_dev, 0x6A, ~0xffffffff, 0x00020000);
/* NBMISIND:0x40 Bit[8]=1 and Bit[10]=1 following bits are required to set in order to allow LVDS or PWM features to work. */
set_nbmisc_enable_bits(nb_dev, 0x40, ~0xffffffff, 0x00000500);
/* NBMISIND:0xC Bit[13]=1 Enable GSM mode for C1e or C3 with pop-up. */
set_nbmisc_enable_bits(nb_dev, 0x0C, ~0xffffffff, 0x00002000);
/* Set NBMISIND:0x1F[3] to map NB F2 interrupt pin to INTB# */
set_nbmisc_enable_bits(nb_dev, 0x1F, ~0xffffffff, 0x00000008);
/* Compliant with CIM_33's MISC_INIT_TBL, except Hide NB_BAR3_PCIE
* Enable access to DEV8
* Enable setPower message for all ports
*/
set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, 1 << 6);
set_nbmisc_enable_bits(nb_dev, 0x0b, 1 << 20, 1 << 20);
set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20, 1 << 20);
set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20, 1 << 20);
set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20, 1 << 20);
set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20, 1 << 20);
set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20, 1 << 20);
set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20, 1 << 20);
//VGA lycheng
set_nbmisc_enable_bits(nb_dev, 0x5D, 1 << 20, 1 << 20);
set_nbmisc_enable_bits(nb_dev, 0x5F, 1 << 20, 1 << 20);
set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7);
set_nbmisc_enable_bits(nb_dev, 0x07, 0x000000f0, 0x30);
/* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */
set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x500180);
printk_info("exit rs780_por_misc_index_init\n");
}
void rs780_por_pcicfg_init(device_t nb_tag)
{
printk_info("enter rs780_por_pcicfg_init\n");
/* enable PCI Memory Access */
set_nbcfg_enable_bits_8(nb_tag, 0x04, (u8)(~0xfd), 0x02);
/* Set RCRB Enable */
set_nbcfg_enable_bits_8(nb_tag, 0x84, (u8)(~0xFF), 0x1);
/* allow decode of 640k-1MB */
set_nbcfg_enable_bits_8(nb_tag, 0x84, (u8)(~0xEF), 0x10);
#if 1
/* Enable PM2_CNTL(BAR2) IO mapped cfg write access to be broadcast to both NB and SB */
set_nbcfg_enable_bits_8(nb_tag, 0x84, (u8)(~0xFF), 0x4);
/* Power Management Register Enable */
set_nbcfg_enable_bits_8(nb_tag, 0x84, (u8)(~0xFF), 0x80);
/* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge
* Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
* BMMsgEn */
//set_nbcfg_enable_bits_8(nb_tag, 0x4C, (u8)(~0x00), 0x42 | 1);
//lycheng disable APIC_ENABLE
set_nbcfg_enable_bits_8(nb_tag, 0x4C, (u8)(~0x00), 0x40 | 1);
/* Reg4Ch[16]=1 (WakeC2En) enable Wake_from_C2 message generation.
* Reg4Ch[18]=1 (P4IntEnable) Enable north-bridge to accept MSI with address 0xFEEx_xxxx from south-bridge */
//set_nbcfg_enable_bits_8(nb_tag, 0x4E, (u8)(~0xFF), 0x05);
//lycheng disable P4IntEnable
set_nbcfg_enable_bits_8(nb_tag, 0x4E, (u8)(~0xFF), 0x01);
#endif
/* Reg94h[4:0] = 0x0 P drive strength offset 0
* Reg94h[6:5] = 0x2 P drive strength additive adjust */
set_nbcfg_enable_bits_8(nb_tag, 0x94, (u8)(~0x80), 0x40);
/* Reg94h[20:16] = 0x0 N drive strength offset 0
* Reg94h[22:21] = 0x2 N drive strength additive adjust */
set_nbcfg_enable_bits_8(nb_tag, 0x96, (u8)(~0x80), 0x40);
/* Reg80h[4:0] = 0x0 Termination offset
* Reg80h[6:5] = 0x2 Termination additive adjust */
set_nbcfg_enable_bits_8(nb_tag, 0x80, (u8)(~0x80), 0x40);
/* Reg80h[14] = 0x1 Enable receiver termination control */
set_nbcfg_enable_bits_8(nb_tag, 0x81, (u8)(~0xFF), 0x40);
/* Reg94h[15] = 0x1 Enables HT transmitter advanced features to be turned on
* Reg94h[14] = 0x1 Enable drive strength control */
set_nbcfg_enable_bits_8(nb_tag, 0x95, (u8)(~0x3F), 0xC4);
/* Reg94h[31:29] = 0x7 Enables HT transmitter de-emphasis */
set_nbcfg_enable_bits_8(nb_tag, 0x97, (u8)(~0x1F), 0xE0);
/*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR,
* force this BAR as mem type in rs780_gfx.c */
set_nbcfg_enable_bits_8(nb_tag, 0x8D, (u8)(~0xFF), 0x03);
printk_info("exit rs780_por_pcicfg_init\n");
}
void pmem_info_initialize(struct bittern_cache *bc)
{
struct pmem_info *ps = &bc->bc_papi.papi_stats;
printk_info("%p: enter\n", bc);
ASSERT(bc != NULL);
ASSERT(bc->bc_magic1 == BC_MAGIC1);
ps->restore_header_valid = 0;
ps->restore_header0_valid = 0;
ps->restore_header1_valid = 0;
ps->restore_corrupt_metadata_blocks = 0;
ps->restore_valid_clean_metadata_blocks = 0;
ps->restore_valid_dirty_metadata_blocks = 0;
ps->restore_invalid_metadata_blocks = 0;
ps->restore_pending_metadata_blocks = 0;
ps->restore_invalid_data_blocks = 0;
ps->restore_valid_clean_data_blocks = 0;
ps->restore_valid_dirty_data_blocks = 0;
ps->restore_hash_corrupt_metadata_blocks = 0;
ps->restore_hash_corrupt_data_blocks = 0;
atomic_set(&ps->metadata_read_async_count, 0);
atomic_set(&ps->metadata_write_async_count, 0);
atomic_set(&ps->data_get_put_page_pending_count, 0);
atomic_set(&ps->data_get_page_read_count, 0);
atomic_set(&ps->data_put_page_read_count, 0);
atomic_set(&ps->data_get_page_write_count, 0);
atomic_set(&ps->data_put_page_write_count, 0);
atomic_set(&ps->data_put_page_write_metadata_count, 0);
atomic_set(&ps->data_convert_page_read_to_write_count, 0);
atomic_set(&ps->data_clone_read_page_to_write_page_count, 0);
cache_timer_init(&ps->metadata_read_async_timer);
cache_timer_init(&ps->metadata_write_async_timer);
cache_timer_init(&ps->data_get_page_read_timer);
cache_timer_init(&ps->data_get_page_read_async_timer);
cache_timer_init(&ps->data_get_page_write_timer);
cache_timer_init(&ps->data_put_page_read_timer);
cache_timer_init(&ps->data_put_page_write_async_timer);
cache_timer_init(&ps->data_put_page_write_async_metadata_timer);
cache_timer_init(&ps->data_put_page_write_timer);
atomic_set(&ps->pmem_read_not4k_count, 0);
atomic_set(&ps->pmem_read_not4k_pending, 0);
atomic_set(&ps->pmem_write_not4k_count, 0);
atomic_set(&ps->pmem_write_not4k_pending, 0);
atomic_set(&ps->pmem_read_4k_count, 0);
atomic_set(&ps->pmem_read_4k_pending, 0);
atomic_set(&ps->pmem_write_4k_count, 0);
atomic_set(&ps->pmem_write_4k_pending, 0);
cache_timer_init(&ps->pmem_read_not4k_timer);
cache_timer_init(&ps->pmem_write_not4k_timer);
cache_timer_init(&ps->pmem_read_4k_timer);
cache_timer_init(&ps->pmem_write_4k_timer);
atomic_set(&ps->pmem_make_req_wq_count, 0);
cache_timer_init(&ps->pmem_make_req_wq_timer);
printk_info("%p: done\n", bc);
}
/*! allocate PMEM resources */
int pmem_allocate(struct bittern_cache *bc, struct block_device *blockdev)
{
const struct cache_papi_interface *pp;
int ret;
struct pmem_api *pa = &bc->bc_papi;
ASSERT(pa->papi_interface == NULL);
bc->bc_pmem_update_workqueue = alloc_workqueue("b_pu/%s",
WQ_MEM_RECLAIM,
1,
bc->bc_name);
if (bc->bc_pmem_update_workqueue == NULL) {
printk_err("%s: cannot allocate pmem_update workqueue\n",
bc->bc_name);
return -ENOMEM;
}
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)
/* direct_access() calling convention changed in 4.0 */
if (blockdev->bd_disk->fops->direct_access != NULL) {
printk_info("%s: detected direct_access-based pmem API implementation\n",
bc->bc_name);
ret = pmem_allocate_papi_mem(bc, blockdev);
pp = &cache_papi_mem;
} else
#endif /* LINUX_VERSION_CODE >= 4.0.0 */
{
printk_info("%s: detected blockdev-based pmem API implementation\n",
bc->bc_name);
ret = pmem_allocate_papi_block(bc, blockdev);
pp = &cache_papi_block;
}
if (ret != 0) {
destroy_workqueue(bc->bc_pmem_update_workqueue);
bc->bc_pmem_update_workqueue = NULL;
printk_err("%s: %s: allocate_func error: ret=%d\n",
bc->bc_name,
pp->interface_name,
ret);
return ret;
}
printk_info("%s: %s: allocate_func ok\n",
bc->bc_name,
pp->interface_name);
ASSERT(pa->papi_bdev_size_bytes > 0);
ASSERT(pa->papi_bdev != NULL);
/*
* everything ok, record index and context
*/
pa->papi_interface = pp;
return 0;
}
void pmem_info_deinitialize(struct bittern_cache *bc)
{
struct pmem_info *ps = &bc->bc_papi.papi_stats;
printk_info("%p: enter\n", bc);
ASSERT(bc != NULL);
ASSERT(bc->bc_magic1 == BC_MAGIC1);
printk_info("%p: data_get_put_page_pending_count=%u\n",
bc, atomic_read(&ps->data_get_put_page_pending_count));
ASSERT(atomic_read(&ps->data_get_put_page_pending_count) == 0);
printk_info("%p: done\n", bc);
}
/*****************************************
* Compliant with CIM_33's ATINB_MCIndex_POR_TABLE
*****************************************/
static void rs780_por_mc_index_init(device_t nb_dev)
{
printk_info("enter rs780_por_mc_index_init\n");
set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F);
set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060);
set_nbmc_enable_bits(nb_dev, 0xD9, ~0x00000000, 0x00600060);
set_nbmc_enable_bits(nb_dev, 0xE0, ~0x00000000, 0x00000000);
set_nbmc_enable_bits(nb_dev, 0xE1, ~0x00000000, 0x00000000);
set_nbmc_enable_bits(nb_dev, 0xE8, ~0x00000000, 0x003E003E);
set_nbmc_enable_bits(nb_dev, 0xE9, ~0x00000000, 0x003E003E);
printk_info("exit rs780_por_mc_index_init\n");
}
void rs780_after_pci_fixup(void) {
device_t dev;
/* bus0, dev0, fun0; */
dev = _pci_make_tag(0, 0, 0);
rs780_enable(dev);
#if 1
/* bus0, dev1, APC. */
printk_info("Bus-0, Dev-1, Fun-0.\n");
dev = _pci_make_tag(0, 1, 0);
rs780_internal_gfx_init(_pci_make_tag(0,0,0) , _pci_make_tag(0,1,0));
rs780_enable(dev);
/* bus0, dev2,3, two GFX */
printk_info("Bus-0, Dev-2, Fun-0\n");
dev = _pci_make_tag(0, 2, 0);
rs780_enable(dev);
printk_info("Bus-0, Dev-3, Fun-0\n");
dev = _pci_make_tag(0, 3, 0);
set_nbmisc_enable_bits(_pci_make_tag(0, 0, 0), 0x0c, 1 << 3,0 << 3);
rs780_gfx_3_init(_pci_make_tag(0, 0, 0), dev, 3);
/* bus0, dev4-7, four GPPSB */
printk_info("Bus-0, Dev-4, Fun-0\n");
dev = _pci_make_tag(0, 4, 0);
rs780_enable(dev);
printk_info("Bus-0, Dev-5, Fun-0\n");
dev = _pci_make_tag(0, 5, 0);
rs780_enable(dev);
printk_info("Bus-0, Dev-6, Fun-0\n");
dev = _pci_make_tag(0, 6, 0);
rs780_enable(dev);
printk_info("Bus-0, Dev-7, Fun-0\n");
dev = _pci_make_tag(0, 7, 0);
rs780_enable(dev);
/* bus 0, dev 9,10, GPP */
printk_info("Bus-0, Dev-9, Fun-0\n");
dev = _pci_make_tag(0, 9, 0);
rs780_enable(dev);
printk_info("Bus-0, Dev-10, Fun-0\n");
dev = _pci_make_tag(0, 10, 0);
rs780_enable(dev);
/* bus0, dev8, SB */
printk_info("Bus-0, Dev-8, Fun-0\n");
dev = _pci_make_tag(0, 8, 0);
rs780_enable(dev);
#endif
}
/*****************************************
* Compliant with CIM_33's ATINB_HTIUNBIND_POR_TABLE
*****************************************/
static void rs780_por_htiu_index_init(device_t nb_dev)
{
printk_info("enter rs780_por_htiu_index_init\n");
//vga lycheng
set_htiu_enable_bits(nb_dev, 0x05, (1<<10|1<<9), 1<<10 | 1<<9);
set_htiu_enable_bits(nb_dev, 0x06, ~0xFFFFFFFE, 0x04203A202);
set_htiu_enable_bits(nb_dev, 0x07, ~0xFFFFFFF9, 0x8001/* | 7 << 8 */); /* fam 10 */
set_htiu_enable_bits(nb_dev, 0x15, ~0xFFFFFFFF, 1<<31| 1<<30 | 1<<27);
set_htiu_enable_bits(nb_dev, 0x1C, ~0xFFFFFFFF, 0xFFFE0000);
set_htiu_enable_bits(nb_dev, 0x4B, (1<<11), 1<<11);
set_htiu_enable_bits(nb_dev, 0x0C, ~0xFFFFFFC0, 1<<0|1<<3);
set_htiu_enable_bits(nb_dev, 0x17, (1<<27|1<<1), 0x1<<1);
set_htiu_enable_bits(nb_dev, 0x17, 0x1 << 30, 0x1<<30);
set_htiu_enable_bits(nb_dev, 0x19, (0xFFFFF+(1<<31)), 0x186A0+(1<<31));
set_htiu_enable_bits(nb_dev, 0x16, (0x3F<<10), 0x7<<10);
set_htiu_enable_bits(nb_dev, 0x23, 0xFFFFFFF, 1<<28);
set_htiu_enable_bits(nb_dev, 0x1E, 0xFFFFFFFF, 0xFFFFFFFF);
/* here we set lower of top of dram2 to 0x0 and enabled*/
printk_info("before lower tom2 is %x, upper tom2 %x\n",
htiu_read_indexN(nb_dev, 0x30),
htiu_read_indexN(nb_dev, 0x31));
htiu_write_indexN(nb_dev, 0x30, 0x01);
htiu_write_indexN(nb_dev, 0x31, 0x80);
/* here we set upper of top of dram2 to 0x0 and enabled, so the top
* of dram 2 is 0x80 0000 0000 = 512GB*/
printk_info("lower tom2 is %x, upper tom2 %x\n",
htiu_read_indexN(nb_dev, 0x30),
htiu_read_indexN(nb_dev, 0x31));
printk_info("exit rs780_por_htiu_index_init\n");
}
/*! deallocate PMEM resources */
void pmem_deallocate(struct bittern_cache *bc)
{
struct pmem_api *pa = &bc->bc_papi;
const struct cache_papi_interface *pp = __pmem_api_interface(pa);
printk_debug("%s: deallocate\n", bc->bc_name);
ASSERT(pa->papi_bdev_size_bytes > 0);
ASSERT(pa->papi_bdev != NULL);
ASSERT(bc->bc_pmem_update_workqueue != NULL);
destroy_workqueue(bc->bc_pmem_update_workqueue);
bc->bc_pmem_update_workqueue = NULL;
printk_info("%s: deallocate_func\n", pp->interface_name);
(*pp->deallocate_func)(bc);
}
void sb700_enable()
{
/*
* 0:11.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3
* 0:12.0 OHCI0-USB1 bit 0 of sm_dev 0x68
* 0:12.1 OHCI1-USB1 bit 1 of sm_dev 0x68
* 0:12.2 EHCI-USB1 bit 2 of sm_dev 0x68
* 0:13.0 OHCI0-USB2 bit 4 of sm_dev 0x68
* 0:13.1 OHCI1-USB2 bit 5 of sm_dev 0x68
* 0:13.2 EHCI-USB2 bit 6 of sm_dev 0x68
* 0:14.5 OHCI0-USB3 bit 7 of sm_dev 0x68
* 0:14.0 SMBUS 0
* 0:14.1 IDE 1
* 0:14.2 HDA bit 3 of pm_io 0x59 : 1 - enable, default + 32 * 4
* 0:14.3 LPC bit 20 of sm_dev 0x64 : 0 - disable, default + 32 * 1
* 0:14.4 PCI 4
*/
#ifdef ENABLE_SATA
printk_info("enable_sata\n");
sb700_sata(1);
#endif
printk_info("enable usb0\n");
sb700_usb(_pci_make_tag(0, 0x12, 0), 1, 0);
printk_info("enable usb1\n");
sb700_usb(_pci_make_tag(0, 0x12, 1), 1, 1);
#if 1
//printk_info("enable usb2\n");
//sb700_usb(_pci_make_tag(0, 0x12, 2), 1, 2);
printk_info("enable usb4\n");
sb700_usb(_pci_make_tag(0, 0x13, 0), 1, 4);
printk_info("enable usb5\n");
sb700_usb(_pci_make_tag(0, 0x13, 1), 1, 5);
//printk_info("enable usb6\n");
//sb700_usb(_pci_make_tag(0, 0x13, 2), 1, 6);
printk_info("enable usb7\n");
sb700_usb(_pci_make_tag(0, 0x14, 5), 1, 7);
#endif
//printk_info("enable hda\n");
//sb700_hda(1);
printk_info("enable lpc\n");
sb700_lpc(1);
//sb700_aci(_pci_make_tag(0, 0x14, 5), 1);
//sb700_mci(_pci_make_tag(0, 0x14, 6), 1);
}
void sb700_after_pci_fixup(void) {
#ifdef ENABLE_SATA
printk_info("sata init\n");
sata_init(_pci_make_tag(0, 0x11, 0));
#endif
printk_info("OHCI0-USB1 init\n");
usb_init(_pci_make_tag(0, 0x12, 0));
printk_info("OHCI1-USB1 init\n");
usb_init(_pci_make_tag(0, 0x12, 1));
#if 1
//printk_info("EHCI-USB1 init\n");
//usb_init2(_pci_make_tag(0, 0x12, 2));
printk_info("OHCI0-USB2 init\n");
usb_init(_pci_make_tag(0, 0x13, 0));
printk_info("OHCI1-USB2 init\n");
usb_init(_pci_make_tag(0, 0x13, 1));
//printk_info("EHCI-USB2 init\n");
//usb_init2(_pci_make_tag(0, 0x13, 2));
printk_info("OHCI0-USB3 init\n");
usb_init(_pci_make_tag(0, 0x14, 5));
#endif
printk_info("lpc init\n");
lpc_init(_pci_make_tag(0, 0x14, 3));
printk_info("ide init\n");
ide_init(_pci_make_tag(0, 0x14, 1));
//vga test
printk_info("pci init\n");
pci_init(_pci_make_tag(0, 0x14, 4));
printk_info("sm init\n");
sm_init(_pci_make_tag(0, 0x14, 0));
#ifdef USE_780E_VGA
printk_info("rs780_internal_gfx_init\n");
internal_gfx_pci_dev_init(_pci_make_tag(0,0,0) , _pci_make_tag(1,0x5,0));
#endif
}
void rs780_enable(device_t dev)
{
device_t nb_dev, sb_dev;
int dev_ind;
nb_dev = _pci_make_tag(0, 0, 0);
sb_dev = _pci_make_tag(0, 8, 0);
_pci_break_tag(dev, NULL, &dev_ind, NULL);
switch(dev_ind) {
case 0:
printk_info("enable_pcie_bar3\n");
enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
printk_info("config_gpp_core\n");
config_gpp_core(nb_dev, sb_dev);
printk_info("rs780_gpp_sb_init\n");
rs780_gpp_sb_init(nb_dev, sb_dev, 8);
/* set SB payload size: 64byte */
printk_info("set sb payload size:64byte\n");
set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPPSB, 3 << 11, 2 << 11);
/* Bus0Dev0Fun1Clock control init, we have to do it here, for dev0 Fun1 doesn't have a vendor or device ID */
//rs780_config_misc_clk(nb_dev);
{ /* BTDC: NBPOR_InitPOR function. */
u8 temp8;
u16 temp16;
u32 temp32;
/* BTDC: Program NB PCI table. */
printk_info("Program NB PCI table\n");
temp16 = pci_read_config16(nb_dev, 0x04);
printk_debug("BTDC: NB_PCI_REG04 = %x.\n", temp16);
temp32 = pci_read_config32(nb_dev, 0x84);
printk_debug("BTDC: NB_PCI_REG84 = %x.\n", temp32);
pci_write_config8(nb_dev, 0x4c, 0x42);
temp8 = pci_read_config8(nb_dev, 0x4e);
temp8 |= 0x05;
pci_write_config8(nb_dev, 0x4e, temp8);
temp32 = pci_read_config32(nb_dev, 0x4c);
printk_debug("BTDC: NB_PCI_REG4C = %x.\n", temp32);
/* BTDC: disable GFX debug. */
printk_info("disable gfx debug\n");
temp8 = pci_read_config8(nb_dev, 0x8d);
temp8 &= ~(1<<1);
pci_write_config8(nb_dev, 0x8d, temp8);
/* BTDC: set temporary NB TOM to 0x40000000. */
//printk_info("set temporary NB TOM to 0xf0000000\n");
//pci_write_config32(nb_dev, 0x90, 0x40000000);
//pci_write_config32(nb_dev, 0x90, 0xf0000000);
printk_info("set temporary NB TOM to 0xffffffff\n");
pci_write_config32(nb_dev, 0x90, 0xffffffff);
/* BTDC: Program NB HTIU table. */
printk_info("Program NB HTIU table\n");
set_htiu_enable_bits(nb_dev, 0x05, 1<<10 | 1<<9, 1<<10|1<<9);
set_htiu_enable_bits(nb_dev, 0x06, 1, 0x4203a202);
set_htiu_enable_bits(nb_dev, 0x07, 1<<1 | 1<<2, 0x8001);
set_htiu_enable_bits(nb_dev, 0x15, 0, 1<<31 | 1<<30 | 1<<27);
set_htiu_enable_bits(nb_dev, 0x1c, 0, 0xfffe0000);
set_htiu_enable_bits(nb_dev, 0x4b, 1<<11, 1<<11);
set_htiu_enable_bits(nb_dev, 0x0c, 0x3f, 1 | 1<<3);
set_htiu_enable_bits(nb_dev, 0x17, 1<<1 | 1<<27, 1<<1);
set_htiu_enable_bits(nb_dev, 0x17, 0, 1<<30);
set_htiu_enable_bits(nb_dev, 0x19, 0xfffff+(1<<31), 0x186a0+(1<<31));
set_htiu_enable_bits(nb_dev, 0x16, 0x3f<<10, 0x7<<10);
set_htiu_enable_bits(nb_dev, 0x23, 0, 1<<28);
/* BTDC: Program NB MISC table. */
printk_info("set NB MISC table\n");
set_nbmisc_enable_bits(nb_dev, 0x0b, 0xffff, 0x00000180);
set_nbmisc_enable_bits(nb_dev, 0x00, 0xffff, 0x00000106);
set_nbmisc_enable_bits(nb_dev, 0x51, 0xffffffff, 0x00100100);
set_nbmisc_enable_bits(nb_dev, 0x53, 0xffffffff, 0x00100100);
set_nbmisc_enable_bits(nb_dev, 0x55, 0xffffffff, 0x00100100);
set_nbmisc_enable_bits(nb_dev, 0x57, 0xffffffff, 0x00100100);
set_nbmisc_enable_bits(nb_dev, 0x59, 0xffffffff, 0x00100100);
set_nbmisc_enable_bits(nb_dev, 0x5b, 0xffffffff, 0x00100100);
set_nbmisc_enable_bits(nb_dev, 0x5d, 0xffffffff, 0x00100100);
set_nbmisc_enable_bits(nb_dev, 0x5f, 0xffffffff, 0x00100100);
set_nbmisc_enable_bits(nb_dev, 0x20, 1<<1, 0);
set_nbmisc_enable_bits(nb_dev, 0x37, 1<<11|1<<12|1<<13|1<<26, 0);
set_nbmisc_enable_bits(nb_dev, 0x68, 1<<5|1<<6, 1<<5);
set_nbmisc_enable_bits(nb_dev, 0x6b, 1<<22, 1<<10);
set_nbmisc_enable_bits(nb_dev, 0x67, 1<<26, 1<<14|1<<10);
set_nbmisc_enable_bits(nb_dev, 0x24, 1<<28|1<<26|1<<25|1<<16, 1<<29|1<<25);
set_nbmisc_enable_bits(nb_dev, 0x38, 1<<24|1<<25, 1<<24);
set_nbmisc_enable_bits(nb_dev, 0x36, 1<<29, 1<<29|1<<28);
set_nbmisc_enable_bits(nb_dev, 0x0c, 0, 1<<13);
set_nbmisc_enable_bits(nb_dev, 0x34, 1<<22, 1<<10);
set_nbmisc_enable_bits(nb_dev, 0x39, 1<<10, 1<<30);
set_nbmisc_enable_bits(nb_dev, 0x22, 1<<3, 0);
set_nbmisc_enable_bits(nb_dev, 0x68, 1<<19, 0);
set_nbmisc_enable_bits(nb_dev, 0x24, 1<<16|1<<17, 1<<17);
set_nbmisc_enable_bits(nb_dev, 0x6a, 1<<22|1<<23, 1<<17|1<<23);
set_nbmisc_enable_bits(nb_dev, 0x35, 1<<21|1<<22, 1<<22);
set_nbmisc_enable_bits(nb_dev, 0x01, 0xffffffff, 0x48);
/* BTDC: the last two step. */
set_nbmisc_enable_bits(nb_dev, 0x01, 1<<8, 1<<8);
set_htiu_enable_bits(nb_dev, 0x2d, 1<<6|1<<4, 1<<6|1<<4);
}
break;
case 1: /* bus0, dev1, APC. */
printk_info("Bus-0, Dev-1, Fun-0.\n");
rs780_internal_gfx_enable(nb_dev,dev);
break;
case 2:
case 3:
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
(1 ? 0 : 1) << dev_ind);
rs780_gfx_init(nb_dev, dev, dev_ind);
break;
case 4: /* bus0, dev4-7, four GPP */
case 5:
case 6:
case 7:
enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
(1 ? 0 : 1) << dev_ind);
rs780_gpp_sb_init(nb_dev, dev, dev_ind);
break;
case 8: /* bus0, dev8, SB */
set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6,
(1 ? 0 : 1) << dev_ind);
rs780_gpp_sb_init(nb_dev, dev, dev_ind);
disable_pcie_bar3(nb_dev);
break;
case 9: /* bus 0, dev 9,10, GPP */
case 10:
enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind),
(1 ? 0 : 1) << (7 + dev_ind));
rs780_gpp_sb_init(nb_dev, dev, dev_ind);
break;
default:
printk_debug("unknown dev: %s\n", dev_ind);
}
}
/*
* Compliant with CIM_48's sbPciCfg.
* Add any south bridge setting.
*/
static void sb700_pci_cfg()
{
device_t dev;
u8 byte;
/* SMBus Device, BDF:0-20-0 */
//dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
dev = _pci_make_tag(0, 20, 0);
#if 1
/* Enable watchdog decode timer */
printk_info("enable watchdog decode timer\n");
byte = pci_read_config8(dev, 0x41);
byte |= (1 << 3);
pci_write_config8(dev, 0x41, byte);
/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
* generated PCIRST#. */
byte = pmio_read(0x65);
byte |= (1 << 4);
pmio_write(0x65, byte);
#endif
/* IDE Device, BDF:0-20-1 */
//dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
dev = _pci_make_tag(0, 20, 1);
/* Enable IDE Explicit prefetch, 0x63[0] clear */
printk_info("enable IDE explicit prefetch\n");
byte = pci_read_config8(dev, 0x63);
byte &= 0xfe;
pci_write_config8(dev, 0x63, byte);
/* LPC Device, BDF:0-20-3 */
//dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
dev = _pci_make_tag(0, 20, 3);
/* rpr7.2 Enabling LPC DMA function. */
printk_info("enabling lpc dma function\n");
byte = pci_read_config8(dev, 0x40);
byte |= (1 << 2);
pci_write_config8(dev, 0x40, byte);
/* rpr7.3 Disabling LPC TimeOut. 0x48[7] clear. */
printk_info("disable lpc timeout\n");
byte = pci_read_config8(dev, 0x48);
byte &= 0x7f;
pci_write_config8(dev, 0x48, byte);
/* rpr7.5 Disabling LPC MSI Capability, 0x78[1] clear. */
printk_info("disable LPC MSI Capability\n");
byte = pci_read_config8(dev, 0x78);
byte &= 0xfd;
pci_write_config8(dev, 0x78, byte);
#ifdef ENABLE_SATA
/* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
//dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
dev = _pci_make_tag(0, 17, 0);
/* rpr7.12 SATA MSI and D3 Power State Capability.
* TODO: We assume S1 is supported. What if it isn't support? */
byte = pci_read_config8(dev, 0x40);
byte |= 1 << 0;
pci_write_config8(dev, 0x40, byte);
if (get_sb700_revision() <= 0x12)
pci_write_config8(dev, 0x34, 0x70);
else
pci_write_config8(dev, 0x34, 0x50);
byte &= ~(1 << 0);
pci_write_config8(dev, 0x40, byte);
#endif
/* TODO: There are several pairs of USB devices.
* Two 4396s, two 4397s, two 4398s.
* The code below only set one of each two. The other
* will be done in sb700_usb.c after all.
* So we don't take the trouble to set them both. */
/* EHCI Device, BDF:0-19-2, ehci usb controller */
//dev = pci_locate_device(PCI_ID(0x1002, 0x4396), 0);
dev = _pci_make_tag(0, 19, 2);
/* rpr6.16 Disabling USB EHCI MSI Capability. 0x50[6]. */
byte = pci_read_config8(dev, 0x50);
byte |= (1 << 6);
pci_write_config8(dev, 0x50, byte);
//lycheng add disabling usb ohci and ehci msi capability
/* EHCI Device, BDF:0-18-2, ehci usb controller */
//dev = pci_locate_device(PCI_ID(0x1002, 0x4396), 0);
dev = _pci_make_tag(0, 18, 2);
/* rpr6.16 Disabling USB EHCI MSI Capability. 0x50[6]. */
byte = pci_read_config8(dev, 0x50);
byte |= (1 << 6);
pci_write_config8(dev, 0x50, byte);
/* OHCI0 Device, BDF:0-19-0, ohci usb controller #0 */
//dev = pci_locate_device(PCI_ID(0x1002, 0x4387), 0);
dev = _pci_make_tag(0, 19, 0);
/* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */
printk_info("disable USB OHCI MSI Capability\n");
byte = pci_read_config8(dev, 0x41);
byte |= 0x3;
pci_write_config8(dev, 0x41, byte);
dev = _pci_make_tag(0, 18, 0);
/* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */
printk_info("disable USB OHCI MSI Capability\n");
byte = pci_read_config8(dev, 0x41);
byte |= 0x3;
pci_write_config8(dev, 0x41, byte);
/* OHCI0 Device, BDF:0-19-1, ohci usb controller #0 */
//dev = pci_locate_device(PCI_ID(0x1002, 0x4398), 0);
dev = _pci_make_tag(0, 19, 1);
byte = pci_read_config8(dev, 0x41);
byte |= 0x3;
pci_write_config8(dev, 0x41, byte);
dev = _pci_make_tag(0, 18, 1);
byte = pci_read_config8(dev, 0x41);
byte |= 0x3;
pci_write_config8(dev, 0x41, byte);
/* OHCI0 Device, BDF:0-20-5, ohci usb controller #0 */
//dev = pci_locate_device(PCI_ID(0x1002, 0x4399), 0);
dev = _pci_make_tag(0, 20, 5);
byte = pci_read_config8(dev, 0x41);
byte |= 0x3;
pci_write_config8(dev, 0x41, byte);
}
int __pmem_header_restore(struct bittern_cache *bc,
int header_block_number,
uint64_t *out_xid)
{
uint32_t header_block_offset_bytes;
uint128_t computed_hash;
int ret;
struct pmem_api *pa = &bc->bc_papi;
struct pmem_header *pm = &pa->papi_hdr;
M_ASSERT(bc != NULL);
M_ASSERT(sizeof(struct pmem_header) == PAGE_SIZE);
M_ASSERT(header_block_number == 0 || header_block_number == 1);
M_ASSERT(bc != NULL);
ASSERT(pa->papi_bdev_size_bytes > 0);
ASSERT(pa->papi_bdev != NULL);
ASSERT(pmem_cache_layout(bc) == CACHE_LAYOUT_INTERLEAVED ||
pmem_cache_layout(bc) == CACHE_LAYOUT_SEQUENTIAL);
header_block_offset_bytes = header_block_number == 0 ?
CACHE_MEM_HEADER_0_OFFSET_BYTES :
CACHE_MEM_HEADER_1_OFFSET_BYTES;
printk_info("[%d]: header_block_offset_bytes=%u\n",
header_block_number, header_block_offset_bytes);
/*
* load requested block
*/
M_ASSERT(sizeof(struct pmem_header) <= PAGE_SIZE);
ret = pmem_read_sync(bc,
header_block_offset_bytes,
pm,
sizeof(struct pmem_header));
/*TODO_ADD_ERROR_INJECTION*/
if (ret != 0) {
ASSERT(ret < 0);
BT_DEV_TRACE(BT_LEVEL_ERROR, bc, NULL, NULL, NULL, NULL,
"pmem_read_sync failed, ret=%d",
ret);
printk_err("%s: pmem_read_sync failed, ret=%d\n",
bc->bc_name,
ret);
return ret;
}
/*TODO_ADD_ERROR_INJECTION*/
if (pm->lm_magic != LM_MAGIC) {
printk_err("[%d]: magic number invalid (0x%x/0x%x)\n",
header_block_number,
pm->lm_magic,
LM_MAGIC);
return -EBADMSG;
}
/*TODO_ADD_ERROR_INJECTION*/
if (pm->lm_version != LM_VERSION) {
printk_err("[%d]: error: version number is incorrect %d/%d\n",
header_block_number, pm->lm_version, LM_VERSION);
return -EBADMSG;
}
computed_hash = murmurhash3_128(pm, PMEM_HEADER_HASHING_SIZE);
/*TODO_ADD_ERROR_INJECTION*/
if (uint128_ne(computed_hash, pm->lm_hash)) {
printk_err("[%d]: hash mismatch: stored_hash=" UINT128_FMT ", computed_hash" UINT128_FMT "\n",
header_block_number,
UINT128_ARG(pm->lm_hash),
UINT128_ARG(computed_hash));
return -EBADMSG;
}
printk_info("[%d]: stored_hash=" UINT128_FMT ", computed_hash" UINT128_FMT "\n",
header_block_number,
UINT128_ARG(pm->lm_hash),
UINT128_ARG(computed_hash));
printk_info("[%d]: restore: xid_first=%llu, xid_current=%llu: %llu\n",
header_block_number,
pm->lm_xid_first,
pm->lm_xid_current, cache_xid_get(bc));
*out_xid = pm->lm_xid_current;
return 0;
}
u8 pm2_ioread(u8 reg)
{
printk_info("pm2_ioread\n");
return pmio_read_index(PM2_INDEX, reg);
}
void pmem_initialize_pmem_header_sizes(struct bittern_cache *bc,
uint64_t device_cache_size_bytes)
{
struct pmem_api *pa = &bc->bc_papi;
struct pmem_header *pm = &pa->papi_hdr;
size_t data_metadata_size;
size_t cache_blocks;
ASSERT(sizeof(struct pmem_header) <= PAGE_SIZE);
ASSERT(device_cache_size_bytes > 0);
ASSERT(pmem_cache_layout(bc) == CACHE_LAYOUT_INTERLEAVED ||
pmem_cache_layout(bc) == CACHE_LAYOUT_SEQUENTIAL);
printk_info("device_cache_size_bytes=%llu (0x%llx) (%llu mbytes)\n",
device_cache_size_bytes,
device_cache_size_bytes,
(device_cache_size_bytes / 1024 / 1024));
printk_info("sizeof (struct pmem_header) = %lu\n",
sizeof(struct pmem_header));
printk_info("sizeof (struct pmem_block_metadata) = %lu\n",
sizeof(struct pmem_block_metadata));
/*
* The code which calculates the number of cache blocks has an
* implicit assumption of having the cache device size being
* a multiple of PAGE_SIZE.
*
* Rather modifying the code to deal with this, we just round down
* the cache size to the nearest NAND flash erase block just to be nice
* to the hardware.
*/
data_metadata_size = round_down(device_cache_size_bytes,
CACHE_NAND_FLASH_ERASE_BLOCK_SIZE);
printk_info("data_metadata_size = %lu (rounded down)\n",
data_metadata_size);
M_ASSERT(data_metadata_size > 0);
data_metadata_size -= CACHE_MEM_FIRST_OFFSET_BYTES;
printk_info("data_metadata_size = %lu (after header subtract)\n",
data_metadata_size);
M_ASSERT(data_metadata_size > 0);
pm->lm_cache_block_size = PAGE_SIZE;
pm->lm_header_size_bytes = sizeof(struct pmem_header);
pm->lm_first_offset_bytes = CACHE_MEM_FIRST_OFFSET_BYTES;
if (pmem_cache_layout(bc) == CACHE_LAYOUT_SEQUENTIAL) {
pm->lm_cache_layout = CACHE_LAYOUT_SEQUENTIAL;
/*
* +---------------------------------------------+
* | hdr0 hdr1 metadata_blocks data_blocks |
* +---------------------------------------------+
*/
if (pmem_page_size_transfer_only(bc))
pm->lm_mcb_size_bytes = PAGE_SIZE;
else
pm->lm_mcb_size_bytes =
sizeof(struct pmem_block_metadata);
printk_info("pm->lm_mcb_size_bytes = %llu\n",
pm->lm_mcb_size_bytes);
/*
* This calculation will break if the device size is not
* a multiple of PAGE_SIZE in the case in which the metadata
* size is not PAGE_SIZE.
* The code above truncates the cache size to megabyte boundary,
* there is no need for truncation here.
*/
cache_blocks = data_metadata_size /
((uint64_t)PAGE_SIZE + pm->lm_mcb_size_bytes);
pm->lm_cache_blocks = cache_blocks;
printk_info("pm->lm_cache_blocks = %llu\n", pm->lm_cache_blocks);
pm->lm_first_offset_bytes = CACHE_MEM_FIRST_OFFSET_BYTES;
pm->lm_first_data_block_offset_bytes =
pm->lm_first_offset_bytes +
(cache_blocks * pm->lm_mcb_size_bytes);
pm->lm_first_data_block_offset_bytes =
round_up(pm->lm_first_data_block_offset_bytes, (uint64_t)PAGE_SIZE);
ASSERT(pm->lm_first_offset_bytes <
pm->lm_first_data_block_offset_bytes);
pm->lm_cache_size_bytes = pm->lm_first_data_block_offset_bytes;
pm->lm_cache_size_bytes += (cache_blocks * (uint64_t)PAGE_SIZE);
printk_info("pm->lm_cache_size_bytes = %llu\n",
pm->lm_cache_size_bytes);
} else {
pm->lm_cache_layout = CACHE_LAYOUT_INTERLEAVED;
/*
* +---------------------------------------------+
* | hdr0 hdr1 (data_metadata_pair)_blocks |
* +---------------------------------------------+
*/
/* 'I' layout only makes sense for page_size transfers only */
ASSERT(pmem_page_size_transfer_only(bc));
pm->lm_mcb_size_bytes = PAGE_SIZE;
printk_info("pm->lm_mcb_size_bytes = %llu\n",
pm->lm_mcb_size_bytes);
cache_blocks = data_metadata_size / ((uint64_t)PAGE_SIZE * 2);
pm->lm_cache_blocks = cache_blocks;
printk_info("pm->lm_cache_blocks = %llu\n",
pm->lm_cache_blocks);
pm->lm_first_offset_bytes = CACHE_MEM_FIRST_OFFSET_BYTES;
pm->lm_first_data_block_offset_bytes =
CACHE_MEM_FIRST_OFFSET_BYTES;
pm->lm_cache_size_bytes = pm->lm_first_offset_bytes;
pm->lm_cache_size_bytes += cache_blocks *
((uint64_t)PAGE_SIZE * 2);
printk_info("pm->lm_cache_size_bytes = %llu\n",
pm->lm_cache_size_bytes);
}
printk_info("cache_layout('%c'): cache_blocks = %lu\n",
pm->lm_cache_layout,
cache_blocks);
ASSERT(cache_blocks > 0);
ASSERT(pm->lm_first_offset_bytes == CACHE_MEM_FIRST_OFFSET_BYTES);
ASSERT(pm->lm_first_offset_bytes <=
pm->lm_first_data_block_offset_bytes);
ASSERT(pm->lm_first_data_block_offset_bytes < pm->lm_cache_size_bytes);
ASSERT(pm->lm_mcb_size_bytes == sizeof(struct pmem_block_metadata) ||
pm->lm_mcb_size_bytes == PAGE_SIZE);
printk_info("pm->lm_cache_size_bytes = %llu (%llu mbytes)\n",
pm->lm_cache_size_bytes,
pm->lm_cache_size_bytes / (1024ULL * 1024ULL));
printk_info("device_cache_size_bytes = %llu (%llu mbytes)\n",
device_cache_size_bytes,
device_cache_size_bytes / (1024ULL * 1024ULL));
M_ASSERT(pm->lm_cache_size_bytes <= device_cache_size_bytes);
}
int pmem_header_initialize(struct bittern_cache *bc)
{
int ret;
struct pmem_api *pa = &bc->bc_papi;
struct pmem_header *pm = &pa->papi_hdr;
size_t cache_size_bytes;
ASSERT(bc != NULL);
ASSERT(pa->papi_bdev_size_bytes > 0);
ASSERT(pa->papi_bdev != NULL);
ASSERT(sizeof(struct pmem_header) == PAGE_SIZE);
cache_size_bytes = pa->papi_bdev_size_bytes;
printk_info("cache_size_bytes=%lu, cache_size_mbytes=%lu\n",
cache_size_bytes, cache_size_bytes / (1024 * 1024));
memset(pm, 0, sizeof(struct pmem_header));
pm->lm_magic = LM_MAGIC;
pm->lm_version = LM_VERSION;
pm->lm_cache_block_size = PAGE_SIZE;
printk_info("pmem_layout='%c'\n", pmem_cache_layout(bc));
ASSERT(pmem_cache_layout(bc) == CACHE_LAYOUT_INTERLEAVED ||
pmem_cache_layout(bc) == CACHE_LAYOUT_SEQUENTIAL);
pmem_initialize_pmem_header_sizes(bc, cache_size_bytes);
ASSERT(LM_NAME_SIZE == sizeof(bc->bc_name));
ASSERT(sizeof(pm->lm_uuid) == 16);
ASSERT(sizeof(pm->lm_device_uuid) == 16);
generate_random_uuid(pm->lm_uuid);
snprintf(pm->lm_name, LM_NAME_SIZE, "%s", bc->bc_name);
generate_random_uuid(pm->lm_device_uuid);
snprintf(pm->lm_device_name,
LM_NAME_SIZE, "%s", bc->bc_cached_device_name);
printk_info("pm->lm_name=%s\n", pm->lm_name);
printk_info("pm->lm_uuid=%pUb\n", pm->lm_uuid);
printk_info("pm->lm_device_name=%s\n", pm->lm_device_name);
printk_info("pm->lm_device_uuid=%pUb\n", pm->lm_device_uuid);
printk_info("pm->lm_cache_size_bytes=%llu\n",
pm->lm_cache_size_bytes);
pm->lm_xid_first = 1ULL;
pm->lm_xid_current = 1ULL;
__pmem_assert_offsets(bc);
/*
* initialize mem copy #0
*/
pm->lm_xid_current++;
pm->lm_hash = murmurhash3_128(pm, PMEM_HEADER_HASHING_SIZE);
ASSERT(sizeof(struct pmem_header) <= PAGE_SIZE);
ret = pmem_write_sync(bc,
CACHE_MEM_HEADER_0_OFFSET_BYTES,
pm,
sizeof(struct pmem_header));
/*TODO_ADD_ERROR_INJECTION*/
if (ret != 0) {
ASSERT(ret < 0);
BT_DEV_TRACE(BT_LEVEL_ERROR, bc, NULL, NULL, NULL, NULL,
"pmem_write_sync header0 failed, ret=%d",
ret);
printk_err("%s: pmem_write_sync header0 failed, ret=%d\n",
bc->bc_name,
ret);
return ret;
}
/*
* initialize mem copy #1
*/
pm->lm_xid_current++;
pm->lm_hash = murmurhash3_128(pm, PMEM_HEADER_HASHING_SIZE);
ASSERT(sizeof(struct pmem_header) <= PAGE_SIZE);
ret = pmem_write_sync(bc,
CACHE_MEM_HEADER_1_OFFSET_BYTES,
pm,
sizeof(struct pmem_header));
/*TODO_ADD_ERROR_INJECTION*/
if (ret != 0) {
ASSERT(ret < 0);
BT_DEV_TRACE(BT_LEVEL_ERROR, bc, NULL, NULL, NULL, NULL,
"pmem_write_sync header0 failed, ret=%d",
ret);
printk_err("%s: pmem_write_sync header0 failed, ret=%d\n",
bc->bc_name,
ret);
return ret;
}
/*
* also initialize xid and bc_buffer_entries
*/
cache_xid_set(bc, pm->lm_xid_current + 1);
printk_info("cache_blocks=%llu\n", pm->lm_cache_blocks);
return 0;
}
int pmem_header_restore(struct bittern_cache *bc)
{
uint64_t hdr_0_xid, hdr_1_xid;
int ret;
struct pmem_api *pa = &bc->bc_papi;
struct pmem_header *pm = &pa->papi_hdr;
ASSERT(bc != NULL);
ASSERT(sizeof(struct pmem_header) == PAGE_SIZE);
ASSERT(bc != NULL);
ASSERT(pa->papi_bdev_size_bytes > 0);
ASSERT(pa->papi_bdev != NULL);
ASSERT(pmem_cache_layout(bc) == CACHE_LAYOUT_INTERLEAVED ||
pmem_cache_layout(bc) == CACHE_LAYOUT_SEQUENTIAL);
/*
* try restore from header #0
*/
ret = __pmem_header_restore(bc, 0, &hdr_0_xid);
printk_info("[0]: ret=%d, hdr_0_xid=%llu\n", ret, hdr_0_xid);
if (ret == 0)
pa->papi_stats.restore_header0_valid = 1;
/*
* try restore from header #1
*/
ret = __pmem_header_restore(bc, 1, &hdr_1_xid);
printk_info("[1]: ret=%d, hdr_1_xid=%llu\n", ret, hdr_1_xid);
if (ret == 0)
pa->papi_stats.restore_header1_valid = 1;
/*
* use the header with the highest xid
*/
if (pa->papi_stats.restore_header0_valid == 0 &&
pa->papi_stats.restore_header1_valid == 0) {
printk_err("error: both headers invalid, ret=%d\n", ret);
M_ASSERT(ret < 0);
return ret;
}
printk_info("hdr_0_xid=%llu\n", hdr_0_xid);
printk_info("hdr_1_xid=%llu\n", hdr_1_xid);
if (pa->papi_stats.restore_header1_valid == 0) {
/* only header0 valid */
printk_info("[0/1]: using hdr_0_xid %llu\n", hdr_0_xid);
ret = __pmem_header_restore(bc, 0, &hdr_0_xid);
printk_info("[0/1]: using hdr_0_xid %llu\n", hdr_0_xid);
cache_xid_set(bc, hdr_0_xid + 1);
} else if (pa->papi_stats.restore_header0_valid == 0) {
/* only header0 valid */
printk_info("[1/0]: using hdr_1_xid %llu\n", hdr_1_xid);
ret = __pmem_header_restore(bc, 1, &hdr_1_xid);
printk_info("[1/0]: using hdr_1_xid %llu\n", hdr_1_xid);
cache_xid_set(bc, hdr_1_xid + 1);
} else if (hdr_0_xid > hdr_1_xid) {
/* both headers valid, use header0 as it has highest xid */
printk_info("[1/1]: using hdr_0_xid=%llu\n", hdr_0_xid);
ret = __pmem_header_restore(bc, 0, &hdr_0_xid);
printk_info("[1/1]: using hdr_0_xid=%llu\n", hdr_0_xid);
cache_xid_set(bc, hdr_0_xid + 1);
} else {
/* both headers valid, use header1 as it's highest or equal */
printk_info("[1/1]: using hdr_1_xid=%llu\n", hdr_1_xid);
ret = __pmem_header_restore(bc, 1, &hdr_1_xid);
printk_info("[1/1]: using hdr_1_xid=%llu\n", hdr_1_xid);
cache_xid_set(bc, hdr_1_xid + 1);
}
/*TODO_ADD_ERROR_INJECTION*/
if (ret != 0) {
printk_err("error: header re-read failed, ret=%d\n", ret);
return ret;
}
M_ASSERT(pa->papi_stats.restore_header0_valid == 1 ||
pa->papi_stats.restore_header1_valid == 1);
cache_xid_inc(bc);
printk_info("bc->bc_xid=%lu\n", atomic64_read(&bc->bc_xid));
printk_info("pm->lm_cache_layout='%c'(0x%x)\n",
pm->lm_cache_layout,
pm->lm_cache_layout);
printk_info("pm->lm_cache_block_size=%llu\n", pm->lm_cache_block_size);
printk_info("pm->lm_xid_current=%llu\n", pm->lm_xid_current);
printk_info("bc->bc_name=%s\n", bc->bc_name);
printk_info("bc->bc_cache_device_name=%s\n", bc->bc_cache_device_name);
printk_info("bc->bc_cached_device_name=%s\n",
bc->bc_cached_device_name);
printk_info("pm->lm_name=%s\n", pm->lm_name);
printk_info("pm->lm_uuid=%pUb\n", pm->lm_uuid);
printk_info("pm->lm_device_name=%s\n", pm->lm_device_name);
printk_info("pm->lm_device_uuid=%pUb\n", pm->lm_device_uuid);
printk_info("pm->lm_cache_size_bytes=%llu\n", pm->lm_cache_size_bytes);
printk_info("pm->lm_mcb_size_bytes=%llu\n", pm->lm_mcb_size_bytes);
/*TODO_ADD_ERROR_INJECTION*/
if (pm->lm_header_size_bytes != sizeof(struct pmem_header)) {
printk_err("lm_header_size mismatch %u/%lu\n",
pm->lm_header_size_bytes,
sizeof(struct pmem_header));
return -EBADMSG;
}
if (pm->lm_cache_block_size != PAGE_SIZE) {
printk_err("lm_header_cache_block_size mismatch %llu/%lu\n",
pm->lm_cache_block_size,
PAGE_SIZE);
return -EBADMSG;
}
if (pm->lm_cache_layout != pmem_cache_layout(bc)) {
printk_err("lm_cache_layout mismatch 0x%x/0x%x\n",
pm->lm_cache_layout,
pmem_cache_layout(bc));
return -EBADMSG;
}
if (pm->lm_mcb_size_bytes != sizeof(struct pmem_block_metadata) &&
pm->lm_mcb_size_bytes != PAGE_SIZE) {
printk_err("lm_mcb_size mismatch %llu:%lu/%lu\n",
pm->lm_mcb_size_bytes,
sizeof(struct pmem_header), PAGE_SIZE);
return -EBADMSG;
}
if (pmem_page_size_transfer_only(bc)) {
if (pm->lm_mcb_size_bytes != PAGE_SIZE) {
printk_err("lm_mcb_size is %llu, provider only hass PAGE_SIZE transfers\n",
pm->lm_mcb_size_bytes);
return -EINVAL;
}
} else {
if (pm->lm_mcb_size_bytes !=
sizeof(struct pmem_block_metadata)) {
printk_err("lm_mcb_size %llu does not match struct\n",
pm->lm_mcb_size_bytes);
return -EINVAL;
}
}
if (pm->lm_first_offset_bytes != CACHE_MEM_FIRST_OFFSET_BYTES) {
printk_err("lm_first_offset_bytes mismatch %llu/%lu\n",
pm->lm_first_offset_bytes,
CACHE_MEM_FIRST_OFFSET_BYTES);
return -EBADMSG;
}
if (pm->lm_cache_layout == CACHE_LAYOUT_SEQUENTIAL) {
uint64_t m = pm->lm_first_offset_bytes;
m += pm->lm_cache_blocks * pm->lm_mcb_size_bytes;
m = round_up(m, PAGE_SIZE);
if (m != pm->lm_first_data_block_offset_bytes) {
printk_err("first_data_block_offset mismatch %llu\n",
pm->lm_first_data_block_offset_bytes);
return -EBADMSG;
}
m += pm->lm_cache_blocks * PAGE_SIZE;
if (m > pm->lm_cache_size_bytes) {
printk_err("last offset exceeds cache size %llu/%llu\n",
m,
pm->lm_cache_size_bytes);
return -EBADMSG;
}
} else {
uint64_t m = pm->lm_first_offset_bytes;
m += pm->lm_cache_blocks * (PAGE_SIZE * 2);
ASSERT(pm->lm_cache_layout == 'I');
if (pm->lm_first_data_block_offset_bytes !=
CACHE_MEM_FIRST_OFFSET_BYTES) {
printk_err("first_data_block_offset mismatch %llu\n",
pm->lm_first_data_block_offset_bytes);
return -EBADMSG;
}
if (m > pm->lm_cache_size_bytes) {
printk_err("last offset exceeds cache size %llu/%llu\n",
m,
pm->lm_cache_size_bytes);
return -EBADMSG;
}
}
ASSERT(pa->papi_bdev_size_bytes > 0);
ASSERT(pa->papi_bdev != NULL);
if (pm->lm_cache_size_bytes < pa->papi_bdev_size_bytes) {
printk_warning("size %llu less than allocated size %lu\n",
pm->lm_cache_size_bytes,
pa->papi_bdev_size_bytes);
printk_warning("size %llumb less than allocated size %llumb\n",
pm->lm_cache_size_bytes / 1024ULL / 1024ULL,
pa->papi_bdev_size_bytes / 1024ULL / 1024ULL);
}
if (pm->lm_cache_size_bytes > pa->papi_bdev_size_bytes) {
printk_err("device size %llu exceeds allocated size %lu\n",
pm->lm_cache_size_bytes,
pa->papi_bdev_size_bytes);
printk_err("device size %llumb exceeds allocated size %llumb\n",
pm->lm_cache_size_bytes / 1024ULL / 1024ULL,
pa->papi_bdev_size_bytes / 1024ULL / 1024ULL);
return -EBADMSG;
}
if (pm->lm_cache_size_bytes == pa->papi_bdev_size_bytes) {
printk_info("device size %llu equals allocated size %lu\n",
pm->lm_cache_size_bytes,
pa->papi_bdev_size_bytes);
printk_info("device size %llumb equals allocated size %llumb\n",
pm->lm_cache_size_bytes / 1024ULL / 1024ULL,
pa->papi_bdev_size_bytes / 1024ULL / 1024ULL);
}
__pmem_assert_offsets(bc);
printk_info("cache '%s' on '%s' restore ok, %llu cache blocks\n",
pm->lm_name,
pm->lm_device_name,
pm->lm_cache_blocks);
pa->papi_stats.restore_header_valid = 1;
return 0;
}
/* sbDevicesPorInitTable */
void sb700_devices_por_init(void)
{
device_t dev;
u8 byte;
/* SMBus Device, BDF:0-20-0 */
dev = _pci_make_tag(0, 20, 0);
/* sbPorAtStartOfTblCfg */
/* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0.
* This is an I/O address. The I/O address must be on 16-byte boundry. */
printk_info("set a-link bridge access address\n");
//pci_write_config32(dev, 0xf0, AB_INDX);
pci_write_config32(dev, 0xf0, 0x00000cd8);
/* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */
/*Enables the SB600 to send transactions upstream over A-Link Express interface. */
printk_info("To enable ab bif dam access\n");
axcfg_reg(0x04, 1 << 2, 1 << 2);
axindxc_reg(0x21, 0xff, 0);
/* 2.3.5:Enabling Non-Posted Memory Write for the K8 Platform */
printk_info("Enabling Non-Posted Memory Write for the K8 Platform\n");
axindxc_reg(0x10, 1 << 9, 1 << 9);
/* END of sbPorAtStartOfTblCfg */
/* sbDevicesPorInitTables */
/* set smbus iobase */
printk_info("set smbus iobase\n");
//pci_write_config32(dev, 0x10, SMBUS_IO_BASE | 1);
//vga lycheng
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
/* enable smbus controller interface */
printk_info("enable smbus controller interface\n");
byte = pci_read_config8(dev, 0xd2);
byte |= (1 << 0);
pci_write_config8(dev, 0xd2, byte);
#if 0
/* set smbus 1, ASF 2.0 (Alert Standard Format), iobase */
printk_info("enable smbus 1, ASF 2.0\n");
pci_write_config16(dev, 0x58, SMBUS_IO_BASE | 0x11);
#endif
/* TODO: I don't know the useage of followed two lines. I copied them from CIM. */
pci_write_config8(dev, 0x0a, 0x1);
pci_write_config8(dev, 0x0b, 0x6);
/* KB2RstEnable */
printk_info("KB2RstEnable\n");
pci_write_config8(dev, 0x40, 0xd4);
/* Enable ISA Address 0-960K decoding */
printk_info("Enable ISA address decoding\n");
pci_write_config8(dev, 0x48, 0x0f);
/* Enable ISA Address 0xC0000-0xDFFFF decode */
printk_info("Enable ISA address 0xc0000-0xdffff decode\n");
pci_write_config8(dev, 0x49, 0xff);
/* Enable decode cycles to IO C50, C51, C52 GPM controls. */
printk_info("Enable decode cycles to IO controls\n");
byte = pci_read_config8(dev, 0x41);
byte &= 0x80;
byte |= 0x33;
pci_write_config8(dev, 0x41, byte);
/* Legacy DMA Prefetch Enhancement, CIM masked it. */
/* pci_write_config8(dev, 0x43, 0x1); */
/* Disabling Legacy USB Fast SMI# */
printk_info("Disabling Legacy USB Fast SMI\n");
byte = pci_read_config8(dev, 0x62);
byte |= 0x24;
pci_write_config8(dev, 0x62, byte);
/* Features Enable */
printk_info("Features Enable\n");
pci_write_config32(dev, 0x64, 0x829E7DBF); /* bit10: Enables the HPET interrupt. */
/* SerialIrq Control */
printk_info("SerialIrq Control\n");
pci_write_config8(dev, 0x69, 0x90);
/* Test Mode, PCIB_SReset_En Mask is set. */
pci_write_config8(dev, 0x6c, 0x20);
/* IO Address Enable, CIM set 0x78 only and masked 0x79. */
printk_info("IO Address Enable\n");
/*pci_write_config8(dev, 0x79, 0x4F); */
pci_write_config8(dev, 0x78, 0xFF);
//#ifndef ENABLE_SATA
#if 1
/* TODO: set ide as primary, if you want to boot from IDE, you'd better set it.Or add a configuration line.*/
printk_info("set ide as primary\n");
byte = pci_read_config8(dev, 0xAD);
byte |= 0x1<<3;
byte &= ~(0x1<<4);
pci_write_config8(dev, 0xAD, byte);
/* This register is not used on sb700. It came from older chipset. */
/*pci_write_config8(dev, 0x95, 0xFF); */
#endif
/* Set smbus iospace enable, I don't know why write 0x04 into reg5 that is reserved */
printk_info("Set smbus iospace enable\n");
pci_write_config16(dev, 0x4, 0x0407);
#if 1
/* clear any lingering errors, so the transaction will run */
printk_info("IO Address Enable\n");
//OUTB(INB(0xba000000 + SMBUS_IO_BASE + SMBHSTSTAT), 0xba000000 + SMBUS_IO_BASE + SMBHSTSTAT);
OUTB(INB(BONITO_PCIIO_BASE_VA + SMBUS_IO_BASE + SMBHSTSTAT), BONITO_PCIIO_BASE_VA + SMBUS_IO_BASE + SMBHSTSTAT);
#endif
/* IDE Device, BDF:0-20-1 */
printk_info("sb700_devices_por_init(): IDE Device, BDF:0-20-1\n");
//dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
dev = _pci_make_tag(0, 20, 1);
/* Disable prefetch */
printk_info("Disable prefetch\n");
byte = pci_read_config8(dev, 0x63);
byte |= 0x1;
pci_write_config8(dev, 0x63, byte);
/* LPC Device, BDF:0-20-3 */
printk_info("sb700_devices_por_init(): LPC Device, BDF:0-20-3\n");
//dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
dev = _pci_make_tag(0, 20, 3);
/* DMA enable */
printk_info("DMA enable\n");
pci_write_config8(dev, 0x40, 0x04);
/* IO Port Decode Enable */
printk_info("IO Port Decode Enable\n");
pci_write_config8(dev, 0x44, 0xFF);
pci_write_config8(dev, 0x45, 0xFF);
pci_write_config8(dev, 0x46, 0xC3);
pci_write_config8(dev, 0x47, 0xFF);
/* IO/Mem Port Decode Enable, I don't know why CIM disable some ports.
* Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f),
* Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65).
* Enable bits for LPC ROM memory address range 1&2 for 1M ROM setting.*/
printk_info("IO/Mem Port Decode Enable\n");
byte = pci_read_config8(dev, 0x48);
byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */
byte |= (1 << 3) | (1 << 4); /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */
byte |= 1 << 6; /* enable for RTC I/O range */
pci_write_config8(dev, 0x48, byte);
pci_write_config8(dev, 0x49, 0xFF);
/* Enable 0x480-0x4bf, 0x4700-0x470B */
byte = pci_read_config8(dev, 0x4A);
byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */
pci_write_config8(dev, 0x4A, byte);
/* Set LPC ROM size, it has been done in sb700_lpc_init().
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB
* pci_write_config16(dev, 0x68, 0x000e)
* pci_write_config16(dev, 0x6c, 0xfff0);*/
/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
printk_info("Enable Tpm12_en and Tpm_legacy\n");
pci_write_config8(dev, 0x7C, 0x05);
/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
* TODO: I don't know what are their mean? */
printk_info("sb700_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
//dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
dev = _pci_make_tag(0, 20, 4);
/* I don't know why CIM tried to write into a read-only reg! */
/*pci_write_config8(dev, 0x0c, 0x20) */ ;
/* Arbiter enable. */
printk_info("Arbiter enable\n");
pci_write_config8(dev, 0x43, 0xff);
/* Set PCDMA request into hight priority list. */
/* pci_write_config8(dev, 0x49, 0x1) */ ;
pci_write_config8(dev, 0x40, 0x26);
/* I don't know why CIM set reg0x1c as 0x11.
* System will block at sdram_initialize() if I set it before call sdram_initialize().
* If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize().
* pci_write_config8(dev, 0x1c, 0x11);
* pci_write_config8(dev, 0x1d, 0x11);*/
/*CIM set this register; but I didn't find its description in RPR.
On DBM690T platform, I didn't find different between set and skip this register.
But on Filbert platform, the DEBUG message from serial port on Peanut board can't be displayed
after the bit0 of this register is set.
pci_write_config8(dev, 0x04, 0x21);
*/
printk_info("CIM set this register\n");
pci_write_config8(dev, 0x0d, 0x40);
pci_write_config8(dev, 0x1b, 0x40);
/* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
printk_info("enable pcib_dual_en_up\n");
pci_write_config8(dev, 0x50, 0x01);
#ifdef ENABLE_SATA
/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
printk_info("sb700_devices_por_init(): SATA Device, BDF:0-17-0\n");
//dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
dev = _pci_make_tag(0, 17, 0);
/*PHY Global Control, we are using A14.
* default: 0x2c40 for ASIC revision A12 and below
* 0x2c00 for ASIC revision A13 and above.*/
printk_info("PHY Global Control\n");
pci_write_config16(dev, 0x86, 0x2C00);
#endif
}
void pm2_iowrite(u8 reg, u8 value)
{
printk_info("pm2_iowrite\n");
pmio_write_index(PM2_INDEX, reg, value);
}
void sb700_pmio_por_init(void)
{
u8 byte;
#if 1
printk_info("sb700_pmio_por_init()\n");
/* K8KbRstEn, KB_RST# control for K8 system. */
byte = pmio_read(0x66);
byte |= 0x20;
pmio_write(0x66, byte);
/* RPR2.31 PM_TURN_OFF_MSG during ASF Shutdown. */
if (get_sb700_revision() <= 0x12) {
byte = pmio_read(0x65);
byte &= ~(1 << 7);
pmio_write(0x65, byte);
byte = pmio_read(0x75);
byte &= 0xc0;
byte |= 0x05;
pmio_write(0x75, byte);
byte = pmio_read(0x52);
byte &= 0xc0;
byte |= 0x08;
pmio_write(0x52, byte);
} else {
byte = pmio_read(0xD7);
byte |= 1 << 0;
pmio_write(0xD7, byte);
byte = pmio_read(0x65);
byte |= 1 << 7;
pmio_write(0x65, byte);
byte = pmio_read(0x75);
byte &= 0xc0;
byte |= 0x01;
pmio_write(0x75, byte);
byte = pmio_read(0x52);
byte &= 0xc0;
byte |= 0x02;
pmio_write(0x52, byte);
}
pmio_write(0x6c, 0xf0);
pmio_write(0x6d, 0x00);
pmio_write(0x6e, 0xc0);
pmio_write(0x6f, 0xfe);
/* rpr2.19: Enabling Spread Spectrum */
printk_info("Enabling Spread Spectrum\n");
byte = pmio_read(0x42);
byte |= 1 << 7;
pmio_write(0x42, byte);
/* TODO: Check if it is necessary. IDE reset */
byte = pmio_read(0xB2);
byte |= 1 << 0;
pmio_write(0xB2, byte);
#endif
}
static void pci_init(device_t dev)
{
u32 dword;
u16 word;
u8 byte;
/* RPR 5.1 Enables the PCI-bridge subtractive decode */
/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
printk_info("Enables the PCI-bridge subtractive decode\n");
byte = pci_read_config8(dev, 0x4B);
byte |= 1 << 7;
pci_write_config8(dev, 0x4B, byte);
byte = pci_read_config8(dev, 0x40);
byte |= 1 << 5;
pci_write_config8(dev, 0x40, byte);
#ifdef USE_780E_VGA
//vga pci card support //lycheng
/* PCI Command: Enable IO response */
byte = pci_read_config8(dev, 0x04);
byte |= (1 << 0)|(1 << 5)|(1 << 1)|(1 << 2);
pci_write_config8(dev, 0x04, byte);
/* PCI Command: VGA enable */
byte = pci_read_config8(dev, 0x3e);
byte |= (1 << 3);
pci_write_config8(dev, 0x3e, byte);
//end vga pci card support
#endif
/* RPR5.2 PCI-bridge upstream dual address window */
/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
printk_info("PCI-bridge upstream dual address window\n");
byte = pci_read_config8(dev, 0x50);
//byte |= 1 << 0;
byte &= ~(1 << 0);
pci_write_config8(dev, 0x50, byte);
/* RPR 5.3 PCI bus 64-byte DMA read access */
/* Enhance the PCI bus DMA performance */
printk_info("PCI bus 64-byte DMA read access\n");
byte = pci_read_config8(dev, 0x4B);
byte |= 1 << 4;
pci_write_config8(dev, 0x4B, byte);
/* RPR 5.4 Enables the PCIB writes to be cacheline aligned. */
/* The size of the writes will be set in the Cacheline Register */
printk_info("Enables the PCIB writes to be cacheline aligned.\n");
byte = pci_read_config8(dev, 0x40);
byte |= 1 << 1;
pci_write_config8(dev, 0x40, byte);
/* RPR 5.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */
printk_info("Enables the PCIB to retain ownership of the bus\n");
pci_write_config8(dev, 0x0D, 0x40);
pci_write_config8(dev, 0x1B, 0x40);
/* RPR 5.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */
printk_info("Enable the command matching checking function\n");
byte = pci_read_config8(dev, 0x4B);
byte |= 1 << 6;
pci_write_config8(dev, 0x4B, byte);
/* RPR 5.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */
printk_info("the PCI arbiter checks for the Bus Idle before asserting GNT#\n");
byte = pci_read_config8(dev, 0x4B);
byte |= 1 << 0;
pci_write_config8(dev, 0x4B, byte);
/* RPR 5.8 Adjusts the GNT# de-assertion time */
printk_info("Adjusts the GNT# de-assertion time\n");
word = pci_read_config16(dev, 0x64);
word |= 1 << 12;
pci_write_config16(dev, 0x64, word);
/* RPR 5.9 Fast Back to Back transactions support */
printk_info("Fast Back to Back transactions support\n");
byte = pci_read_config8(dev, 0x48);
byte |= 1 << 2;
/* pci_write_config8(dev, 0x48, byte); */
/* RPR 5.10 Enable Lock Operation */
/* byte = pci_read_config8(dev, 0x48); */
byte |= 1 << 3;
pci_write_config8(dev, 0x48, byte);
/* RPR 5.11 Enable additional optional PCI clock */
printk_info("Enable additional optional PCI clock\n");
word = pci_read_config16(dev, 0x64);
word |= 1 << 8;
pci_write_config16(dev, 0x64, word);
/* RPR 5.12 Enable One-Prefetch-Channel Mode */
printk_info("Enable One-Prefetch-Channel Mode\n");
dword = pci_read_config32(dev, 0x64);
dword |= 1 << 20;
pci_write_config32(dev, 0x64, dword);
/* RPR 5.13 Disable PCIB MSI Capability */
printk_info("Disable PCIB MSI Capability\n");
byte = pci_read_config8(dev, 0x40);
byte &= ~(1 << 3);
pci_write_config8(dev, 0x40, byte);
/* rpr5.14 Adjusting CLKRUN# */
printk_info("Adjusting CLKRUN\n");
dword = pci_read_config32(dev, 0x64);
dword |= (1 << 15);
pci_write_config32(dev, 0x64, dword);
}
/*!
* This function is used to ASSERT the integrity of the functions
* which compute the metadata and data offsets. For each given
* block id [1 .. N], there is corresponding correct metadata
* offset 'm' and a data offset 'd'. The offets need to be distinct
* (checking that is left to eyeballs), and always contained within
* the cache size, something which we assert on here.
* The called functions have more elaborate checking, so just by
* calling them we test a lot of logic.
*/
void __pmem_assert_offsets(struct bittern_cache *bc)
{
struct pmem_api *pa = &bc->bc_papi;
struct pmem_header *pm = &pa->papi_hdr;
off_t m, d;
uint64_t cache_blocks = pm->lm_cache_blocks;
m = __cache_block_id_2_metadata_pmem_offset(bc, 1);
d = __cache_block_id_2_data_pmem_offset(bc, 1);
printk_info("cache_block #1 m=%lu(%lu), d=%lu(%lu)\n",
m, m / PAGE_SIZE, d, d / PAGE_SIZE);
M_ASSERT(m <= pm->lm_cache_size_bytes);
M_ASSERT(d <= pm->lm_cache_size_bytes);
m = __cache_block_id_2_metadata_pmem_offset(bc, 2);
d = __cache_block_id_2_data_pmem_offset(bc, 2);
printk_info("cache_block #2 m=%lu(%lu), d=%lu(%lu)\n",
m, m / PAGE_SIZE, d, d / PAGE_SIZE);
M_ASSERT(m <= pm->lm_cache_size_bytes);
M_ASSERT(d <= pm->lm_cache_size_bytes);
m = __cache_block_id_2_metadata_pmem_offset(bc, cache_blocks / 2);
d = __cache_block_id_2_data_pmem_offset(bc, cache_blocks / 2);
printk_info("cache_block #cache_blocks/2 m=%lu(%lu), d=%lu(%lu)\n",
m, m / PAGE_SIZE, d, d / PAGE_SIZE);
M_ASSERT(m <= pm->lm_cache_size_bytes);
M_ASSERT(d <= pm->lm_cache_size_bytes);
m = __cache_block_id_2_metadata_pmem_offset(bc, cache_blocks / 2 + 1);
d = __cache_block_id_2_data_pmem_offset(bc, cache_blocks / 2 + 1);
printk_info("cache_block #cache_blocks/2+1 m=%lu(%lu), d=%lu(%lu)\n",
m, m / PAGE_SIZE, d, d / PAGE_SIZE);
M_ASSERT(m <= pm->lm_cache_size_bytes);
M_ASSERT(d <= pm->lm_cache_size_bytes);
m = __cache_block_id_2_metadata_pmem_offset(bc, cache_blocks - 100);
d = __cache_block_id_2_data_pmem_offset(bc, cache_blocks - 100);
printk_info("cache_block #cache_blocks-100 m=%lu(%lu), d=%lu(%lu)\n",
m, m / PAGE_SIZE, d, d / PAGE_SIZE);
M_ASSERT(m <= pm->lm_cache_size_bytes);
M_ASSERT(d <= pm->lm_cache_size_bytes);
m = __cache_block_id_2_metadata_pmem_offset(bc, cache_blocks - 10);
d = __cache_block_id_2_data_pmem_offset(bc, cache_blocks - 10);
printk_info("cache_block #cache_blocks-10 m=%lu(%lu), d=%lu(%lu)\n",
m, m / PAGE_SIZE, d, d / PAGE_SIZE);
M_ASSERT(m <= pm->lm_cache_size_bytes);
M_ASSERT(d <= pm->lm_cache_size_bytes);
m = __cache_block_id_2_metadata_pmem_offset(bc, cache_blocks - 2);
d = __cache_block_id_2_data_pmem_offset(bc, cache_blocks - 2);
printk_info("cache_block #cache_blocks-2 m=%lu(%lu), d=%lu(%lu)\n",
m, m / PAGE_SIZE, d, d / PAGE_SIZE);
M_ASSERT(m <= pm->lm_cache_size_bytes);
M_ASSERT(d <= pm->lm_cache_size_bytes);
m = __cache_block_id_2_metadata_pmem_offset(bc, cache_blocks - 1);
d = __cache_block_id_2_data_pmem_offset(bc, cache_blocks - 1);
printk_info("cache_block #cache_blocks-1 m=%lu(%lu), d=%lu(%lu)\n",
m, m / PAGE_SIZE, d, d / PAGE_SIZE);
M_ASSERT(m <= pm->lm_cache_size_bytes);
M_ASSERT(d <= pm->lm_cache_size_bytes);
m = __cache_block_id_2_metadata_pmem_offset(bc, cache_blocks);
d = __cache_block_id_2_data_pmem_offset(bc, cache_blocks);
printk_info("cache_block #cache_blocks m=%lu(%lu), d=%lu(%lu)\n",
m, m / PAGE_SIZE, d, d / PAGE_SIZE);
M_ASSERT(m <= pm->lm_cache_size_bytes);
M_ASSERT(d <= pm->lm_cache_size_bytes);
}