/*copy colour, depth, & stencil buffers from system memory to graphics memory*/
static unsigned int *build_sys2gmem_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt,
struct gmem_shadow_t *shadow)
{
unsigned int *cmds = shadow->gmem_restore_commands;
unsigned int *start = cmds;
/* Store TP0_CHICKEN register */
*cmds++ = cp_type3_packet(CP_REG_TO_MEM, 2);
*cmds++ = REG_TP0_CHICKEN;
*cmds++ = tmp_ctx.chicken_restore;
*cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
*cmds++ = 0;
/* Set TP0_CHICKEN to zero */
*cmds++ = cp_type0_packet(REG_TP0_CHICKEN, 1);
*cmds++ = 0x00000000;
/* Set PA_SC_AA_CONFIG to 0 */
*cmds++ = cp_type0_packet(REG_PA_SC_AA_CONFIG, 1);
*cmds++ = 0x00000000;
/* shader constants */
/* vertex buffer constants */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 7);
*cmds++ = (0x1 << 16) | (9 * 6);
/* valid(?) vtx constant flag & addr */
*cmds++ = shadow->quad_vertices.gpuaddr | 0x3;
/* limit = 12 dwords */
*cmds++ = 0x00000030;
/* valid(?) vtx constant flag & addr */
*cmds++ = shadow->quad_texcoords.gpuaddr | 0x3;
/* limit = 8 dwords */
*cmds++ = 0x00000020;
*cmds++ = 0;
*cmds++ = 0;
/* Invalidate L2 cache to make sure vertices are updated */
*cmds++ = cp_type0_packet(REG_TC_CNTL_STATUS, 1);
*cmds++ = 0x1;
cmds = program_shader(cmds, 0, sys2gmem_vtx_pgm, SYS2GMEM_VTX_PGM_LEN);
/* Repartition shaders */
*cmds++ = cp_type0_packet(REG_SQ_INST_STORE_MANAGMENT, 1);
*cmds++ = 0x180;
/* Invalidate Vertex & Pixel instruction code address and sizes */
*cmds++ = cp_type3_packet(CP_INVALIDATE_STATE, 1);
*cmds++ = 0x00000300; /* 0x100 = Vertex, 0x200 = Pixel */
*cmds++ = cp_type3_packet(CP_SET_SHADER_BASES, 1);
*cmds++ = adreno_encode_istore_size(adreno_dev)
| adreno_dev->pix_shader_start;
/* Load the patched fragment shader stream */
cmds =
program_shader(cmds, 1, sys2gmem_frag_pgm, SYS2GMEM_FRAG_PGM_LEN);
/* SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_SQ_PROGRAM_CNTL);
*cmds++ = 0x10030002;
*cmds++ = 0x00000008;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_SC_AA_MASK);
*cmds++ = 0x0000ffff; /* REG_PA_SC_AA_MASK */
if (!adreno_is_a22x(adreno_dev)) {
/* PA_SC_VIZ_QUERY */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_SC_VIZ_QUERY);
*cmds++ = 0x0; /*REG_PA_SC_VIZ_QUERY */
}
/* RB_COLORCONTROL */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_COLORCONTROL);
*cmds++ = 0x00000c20;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 4);
*cmds++ = CP_REG(REG_VGT_MAX_VTX_INDX);
*cmds++ = 0x00ffffff; /* mmVGT_MAX_VTX_INDX */
*cmds++ = 0x0; /* mmVGT_MIN_VTX_INDX */
*cmds++ = 0x00000000; /* mmVGT_INDX_OFFSET */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL);
*cmds++ = 0x00000002; /* mmVGT_VERTEX_REUSE_BLOCK_CNTL */
*cmds++ = 0x00000002; /* mmVGT_OUT_DEALLOC_CNTL */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_SQ_INTERPOLATOR_CNTL);
*cmds++ = 0xffffffff; /* mmSQ_INTERPOLATOR_CNTL */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_SC_AA_CONFIG);
*cmds++ = 0x00000000; /* REG_PA_SC_AA_CONFIG */
/* set REG_PA_SU_SC_MODE_CNTL
* Front_ptype = draw triangles
* Back_ptype = draw triangles
* Provoking vertex = last
*/
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_SU_SC_MODE_CNTL);
*cmds++ = 0x00080240;
/* texture constants */
*cmds++ =
cp_type3_packet(CP_SET_CONSTANT, (SYS2GMEM_TEX_CONST_LEN + 1));
*cmds++ = (0x1 << 16) | (0 * 6);
memcpy(cmds, sys2gmem_tex_const, SYS2GMEM_TEX_CONST_LEN << 2);
cmds[0] |= (shadow->pitch >> 5) << 22;
cmds[1] |=
shadow->gmemshadow.gpuaddr | surface_format_table[shadow->format];
cmds[2] |= (shadow->width - 1) | (shadow->height - 1) << 13;
cmds += SYS2GMEM_TEX_CONST_LEN;
/* program surface info */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_RB_SURFACE_INFO);
*cmds++ = shadow->gmem_pitch; /* pitch, MSAA = 1 */
/* RB_COLOR_INFO Endian=none, Linear, Format=RGBA8888, Swap=0,
* Base=gmem_base
*/
*cmds++ =
(shadow->
format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | tmp_ctx.gmem_base;
/* RB_DEPTHCONTROL */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_DEPTHCONTROL);
if (adreno_is_a22x(adreno_dev))
*cmds++ = 8; /* disable Z */
else
*cmds++ = 0; /* disable Z */
/* Use maximum scissor values -- quad vertices already
* have the correct bounds */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_PA_SC_SCREEN_SCISSOR_TL);
*cmds++ = (0 << 16) | 0;
*cmds++ = ((0x1fff) << 16) | 0x1fff;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL);
*cmds++ = (unsigned int)((1U << 31) | (0 << 16) | 0);
*cmds++ = ((0x1fff) << 16) | 0x1fff;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_CL_VTE_CNTL);
/* disable X/Y/Z transforms, X/Y/Z are premultiplied by W */
*cmds++ = 0x00000b00;
/*load the viewport so that z scale = clear depth and z offset = 0.0f */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_PA_CL_VPORT_ZSCALE);
*cmds++ = 0xbf800000;
*cmds++ = 0x0;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_COLOR_MASK);
*cmds++ = 0x0000000f; /* R = G = B = 1:enabled */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_COLOR_DEST_MASK);
*cmds++ = 0xffffffff;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_SQ_WRAPPING_0);
*cmds++ = 0x00000000;
*cmds++ = 0x00000000;
/* load the stencil ref value
* $AAM - do this later
*/
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_MODECONTROL);
/* draw pixels with color and depth/stencil component */
*cmds++ = 0x4;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_CL_CLIP_CNTL);
*cmds++ = 0x00010000;
if (adreno_is_a22x(adreno_dev)) {
*cmds++ = cp_type3_packet(CP_SET_DRAW_INIT_FLAGS, 1);
*cmds++ = 0;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_A220_RB_LRZ_VSC_CONTROL);
*cmds++ = 0x0000000;
*cmds++ = cp_type3_packet(CP_DRAW_INDX, 3);
*cmds++ = 0; /* viz query info. */
/* PrimType=RectList, SrcSel=AutoIndex, VisCullMode=Ignore*/
*cmds++ = 0x00004088;
*cmds++ = 3; /* NumIndices=3 */
} else {
/* queue the draw packet */
*cmds++ = cp_type3_packet(CP_DRAW_INDX, 2);
*cmds++ = 0; /* viz query info. */
/* PrimType=RectList, NumIndices=3, SrcSel=AutoIndex */
*cmds++ = 0x00030088;
}
/* create indirect buffer command for above command sequence */
create_ib1(drawctxt, shadow->gmem_restore, start, cmds);
return cmds;
}
static unsigned int *build_sys2gmem_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt,
struct gmem_shadow_t *shadow)
{
unsigned int *cmds = shadow->gmem_restore_commands;
unsigned int *start = cmds;
if (!(drawctxt->flags & CTXT_FLAGS_PREAMBLE)) {
*cmds++ = cp_type3_packet(CP_REG_TO_MEM, 2);
*cmds++ = REG_TP0_CHICKEN;
*cmds++ = tmp_ctx.chicken_restore;
*cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
*cmds++ = 0;
}
*cmds++ = cp_type0_packet(REG_TP0_CHICKEN, 1);
*cmds++ = 0x00000000;
*cmds++ = cp_type0_packet(REG_PA_SC_AA_CONFIG, 1);
*cmds++ = 0x00000000;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 7);
*cmds++ = (0x1 << 16) | (9 * 6);
*cmds++ = shadow->quad_vertices.gpuaddr | 0x3;
*cmds++ = 0x00000030;
*cmds++ = shadow->quad_texcoords.gpuaddr | 0x3;
*cmds++ = 0x00000020;
*cmds++ = 0;
*cmds++ = 0;
*cmds++ = cp_type0_packet(REG_TC_CNTL_STATUS, 1);
*cmds++ = 0x1;
cmds = program_shader(cmds, 0, sys2gmem_vtx_pgm, SYS2GMEM_VTX_PGM_LEN);
*cmds++ = cp_type0_packet(REG_SQ_INST_STORE_MANAGMENT, 1);
*cmds++ = adreno_dev->pix_shader_start;
*cmds++ = cp_type3_packet(CP_INVALIDATE_STATE, 1);
*cmds++ = 0x00000300;
*cmds++ = cp_type3_packet(CP_SET_SHADER_BASES, 1);
*cmds++ = adreno_encode_istore_size(adreno_dev)
| adreno_dev->pix_shader_start;
cmds =
program_shader(cmds, 1, sys2gmem_frag_pgm, SYS2GMEM_FRAG_PGM_LEN);
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_SQ_PROGRAM_CNTL);
*cmds++ = 0x10030002;
*cmds++ = 0x00000008;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_SC_AA_MASK);
*cmds++ = 0x0000ffff;
if (!adreno_is_a22x(adreno_dev)) {
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_SC_VIZ_QUERY);
*cmds++ = 0x0;
}
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_COLORCONTROL);
*cmds++ = 0x00000c20;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 4);
*cmds++ = CP_REG(REG_VGT_MAX_VTX_INDX);
*cmds++ = 0x00ffffff;
*cmds++ = 0x0;
*cmds++ = 0x00000000;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL);
*cmds++ = 0x00000002;
*cmds++ = 0x00000002;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_SQ_INTERPOLATOR_CNTL);
*cmds++ = 0xffffffff;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_SC_AA_CONFIG);
*cmds++ = 0x00000000;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_SU_SC_MODE_CNTL);
*cmds++ = 0x00080240;
*cmds++ =
cp_type3_packet(CP_SET_CONSTANT, (SYS2GMEM_TEX_CONST_LEN + 1));
*cmds++ = (0x1 << 16) | (0 * 6);
memcpy(cmds, sys2gmem_tex_const, SYS2GMEM_TEX_CONST_LEN << 2);
cmds[0] |= (shadow->pitch >> 5) << 22;
cmds[1] |=
shadow->gmemshadow.gpuaddr | surface_format_table[shadow->format];
cmds[2] |= (shadow->width - 1) | (shadow->height - 1) << 13;
cmds += SYS2GMEM_TEX_CONST_LEN;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_RB_SURFACE_INFO);
*cmds++ = shadow->gmem_pitch;
*cmds++ =
(shadow->
format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | tmp_ctx.gmem_base;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_DEPTHCONTROL);
if (adreno_is_a22x(adreno_dev))
*cmds++ = 8;
else
*cmds++ = 0;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_PA_SC_SCREEN_SCISSOR_TL);
*cmds++ = (0 << 16) | 0;
*cmds++ = ((0x1fff) << 16) | 0x1fff;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL);
*cmds++ = (unsigned int)((1U << 31) | (0 << 16) | 0);
*cmds++ = ((0x1fff) << 16) | 0x1fff;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_CL_VTE_CNTL);
*cmds++ = 0x00000b00;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_PA_CL_VPORT_ZSCALE);
*cmds++ = 0xbf800000;
*cmds++ = 0x0;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_COLOR_MASK);
*cmds++ = 0x0000000f;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_COLOR_DEST_MASK);
*cmds++ = 0xffffffff;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_SQ_WRAPPING_0);
*cmds++ = 0x00000000;
*cmds++ = 0x00000000;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_MODECONTROL);
*cmds++ = 0x4;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_CL_CLIP_CNTL);
*cmds++ = 0x00010000;
if (adreno_is_a22x(adreno_dev)) {
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_A220_RB_LRZ_VSC_CONTROL);
*cmds++ = 0x0000000;
*cmds++ = cp_type3_packet(CP_DRAW_INDX, 3);
*cmds++ = 0;
*cmds++ = 0x00004088;
*cmds++ = 3;
} else {
*cmds++ = cp_type3_packet(CP_DRAW_INDX, 2);
*cmds++ = 0;
*cmds++ = 0x00030088;
}
create_ib1(drawctxt, shadow->gmem_restore, start, cmds);
return cmds;
}
/*copy colour, depth, & stencil buffers from graphics memory to system memory*/
static unsigned int *build_gmem2sys_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt,
struct gmem_shadow_t *shadow)
{
unsigned int *cmds = shadow->gmem_save_commands;
unsigned int *start = cmds;
/* Calculate the new offset based on the adjusted base */
unsigned int bytesperpixel = format2bytesperpixel[shadow->format];
unsigned int addr = shadow->gmemshadow.gpuaddr;
unsigned int offset = (addr - (addr & 0xfffff000)) / bytesperpixel;
/* Store TP0_CHICKEN register */
*cmds++ = cp_type3_packet(CP_REG_TO_MEM, 2);
*cmds++ = REG_TP0_CHICKEN;
*cmds++ = tmp_ctx.chicken_restore;
*cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
*cmds++ = 0;
/* Set TP0_CHICKEN to zero */
*cmds++ = cp_type0_packet(REG_TP0_CHICKEN, 1);
*cmds++ = 0x00000000;
/* Set PA_SC_AA_CONFIG to 0 */
*cmds++ = cp_type0_packet(REG_PA_SC_AA_CONFIG, 1);
*cmds++ = 0x00000000;
/* program shader */
/* load shader vtx constants ... 5 dwords */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 4);
*cmds++ = (0x1 << 16) | SHADER_CONST_ADDR;
*cmds++ = 0;
/* valid(?) vtx constant flag & addr */
*cmds++ = shadow->quad_vertices.gpuaddr | 0x3;
/* limit = 12 dwords */
*cmds++ = 0x00000030;
/* Invalidate L2 cache to make sure vertices are updated */
*cmds++ = cp_type0_packet(REG_TC_CNTL_STATUS, 1);
*cmds++ = 0x1;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 4);
*cmds++ = CP_REG(REG_VGT_MAX_VTX_INDX);
*cmds++ = 0x00ffffff; /* REG_VGT_MAX_VTX_INDX */
*cmds++ = 0x0; /* REG_VGT_MIN_VTX_INDX */
*cmds++ = 0x00000000; /* REG_VGT_INDX_OFFSET */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_SC_AA_MASK);
*cmds++ = 0x0000ffff; /* REG_PA_SC_AA_MASK */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_COLORCONTROL);
*cmds++ = 0x00000c20;
/* Repartition shaders */
*cmds++ = cp_type0_packet(REG_SQ_INST_STORE_MANAGMENT, 1);
*cmds++ = 0x180;
/* Invalidate Vertex & Pixel instruction code address and sizes */
*cmds++ = cp_type3_packet(CP_INVALIDATE_STATE, 1);
*cmds++ = 0x00003F00;
*cmds++ = cp_type3_packet(CP_SET_SHADER_BASES, 1);
*cmds++ = adreno_encode_istore_size(adreno_dev)
| adreno_dev->pix_shader_start;
/* load the patched vertex shader stream */
cmds = program_shader(cmds, 0, gmem2sys_vtx_pgm, GMEM2SYS_VTX_PGM_LEN);
/* Load the patched fragment shader stream */
cmds =
program_shader(cmds, 1, gmem2sys_frag_pgm, GMEM2SYS_FRAG_PGM_LEN);
/* SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_SQ_PROGRAM_CNTL);
if (adreno_is_a22x(adreno_dev))
*cmds++ = 0x10018001;
else
*cmds++ = 0x10010001;
*cmds++ = 0x00000008;
/* resolve */
/* PA_CL_VTE_CNTL */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_CL_VTE_CNTL);
/* disable X/Y/Z transforms, X/Y/Z are premultiplied by W */
*cmds++ = 0x00000b00;
/* program surface info */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_RB_SURFACE_INFO);
*cmds++ = shadow->gmem_pitch; /* pitch, MSAA = 1 */
/* RB_COLOR_INFO Endian=none, Linear, Format=RGBA8888, Swap=0,
* Base=gmem_base
*/
/* gmem base assumed 4K aligned. */
BUG_ON(tmp_ctx.gmem_base & 0xFFF);
*cmds++ =
(shadow->
format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | tmp_ctx.gmem_base;
/* disable Z */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_DEPTHCONTROL);
if (adreno_is_a22x(adreno_dev))
*cmds++ = 0x08;
else
*cmds++ = 0;
/* set REG_PA_SU_SC_MODE_CNTL
* Front_ptype = draw triangles
* Back_ptype = draw triangles
* Provoking vertex = last
*/
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_SU_SC_MODE_CNTL);
*cmds++ = 0x00080240;
/* Use maximum scissor values -- quad vertices already have the
* correct bounds */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_PA_SC_SCREEN_SCISSOR_TL);
*cmds++ = (0 << 16) | 0;
*cmds++ = (0x1fff << 16) | (0x1fff);
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL);
*cmds++ = (unsigned int)((1U << 31) | (0 << 16) | 0);
*cmds++ = (0x1fff << 16) | (0x1fff);
/* load the viewport so that z scale = clear depth and
* z offset = 0.0f
*/
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_PA_CL_VPORT_ZSCALE);
*cmds++ = 0xbf800000; /* -1.0f */
*cmds++ = 0x0;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_COLOR_MASK);
*cmds++ = 0x0000000f; /* R = G = B = 1:enabled */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_COLOR_DEST_MASK);
*cmds++ = 0xffffffff;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_SQ_WRAPPING_0);
*cmds++ = 0x00000000;
*cmds++ = 0x00000000;
/* load the stencil ref value
* $AAM - do this later
*/
/* load the COPY state */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 6);
*cmds++ = CP_REG(REG_RB_COPY_CONTROL);
*cmds++ = 0; /* RB_COPY_CONTROL */
*cmds++ = addr & 0xfffff000; /* RB_COPY_DEST_BASE */
*cmds++ = shadow->pitch >> 5; /* RB_COPY_DEST_PITCH */
/* Endian=none, Linear, Format=RGBA8888,Swap=0,!Dither,
* MaskWrite:R=G=B=A=1
*/
*cmds++ = 0x0003c008 |
(shadow->format << RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT);
/* Make sure we stay in offsetx field. */
BUG_ON(offset & 0xfffff000);
*cmds++ = offset;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_MODECONTROL);
*cmds++ = 0x6; /* EDRAM copy */
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_CL_CLIP_CNTL);
*cmds++ = 0x00010000;
if (adreno_is_a22x(adreno_dev)) {
*cmds++ = cp_type3_packet(CP_SET_DRAW_INIT_FLAGS, 1);
*cmds++ = 0;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_A220_RB_LRZ_VSC_CONTROL);
*cmds++ = 0x0000000;
*cmds++ = cp_type3_packet(CP_DRAW_INDX, 3);
*cmds++ = 0; /* viz query info. */
/* PrimType=RectList, SrcSel=AutoIndex, VisCullMode=Ignore*/
*cmds++ = 0x00004088;
*cmds++ = 3; /* NumIndices=3 */
} else {
/* queue the draw packet */
*cmds++ = cp_type3_packet(CP_DRAW_INDX, 2);
*cmds++ = 0; /* viz query info. */
/* PrimType=RectList, NumIndices=3, SrcSel=AutoIndex */
*cmds++ = 0x00030088;
}
/* create indirect buffer command for above command sequence */
create_ib1(drawctxt, shadow->gmem_save, start, cmds);
return cmds;
}
static unsigned int *build_gmem2sys_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt,
struct gmem_shadow_t *shadow)
{
unsigned int *cmds = shadow->gmem_save_commands;
unsigned int *start = cmds;
unsigned int bytesperpixel = format2bytesperpixel[shadow->format];
unsigned int addr = shadow->gmemshadow.gpuaddr;
unsigned int offset = (addr - (addr & 0xfffff000)) / bytesperpixel;
if (!(drawctxt->flags & CTXT_FLAGS_PREAMBLE)) {
*cmds++ = cp_type3_packet(CP_REG_TO_MEM, 2);
*cmds++ = REG_TP0_CHICKEN;
*cmds++ = tmp_ctx.chicken_restore;
*cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
*cmds++ = 0;
}
*cmds++ = cp_type0_packet(REG_TP0_CHICKEN, 1);
*cmds++ = 0x00000000;
*cmds++ = cp_type0_packet(REG_PA_SC_AA_CONFIG, 1);
*cmds++ = 0x00000000;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 4);
*cmds++ = (0x1 << 16) | SHADER_CONST_ADDR;
*cmds++ = 0;
*cmds++ = shadow->quad_vertices.gpuaddr | 0x3;
*cmds++ = 0x00000030;
*cmds++ = cp_type0_packet(REG_TC_CNTL_STATUS, 1);
*cmds++ = 0x1;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 4);
*cmds++ = CP_REG(REG_VGT_MAX_VTX_INDX);
*cmds++ = 0x00ffffff;
*cmds++ = 0x0;
*cmds++ = 0x00000000;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_SC_AA_MASK);
*cmds++ = 0x0000ffff;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_COLORCONTROL);
*cmds++ = 0x00000c20;
*cmds++ = cp_type0_packet(REG_SQ_INST_STORE_MANAGMENT, 1);
*cmds++ = adreno_dev->pix_shader_start;
*cmds++ = cp_type3_packet(CP_INVALIDATE_STATE, 1);
*cmds++ = 0x00003F00;
*cmds++ = cp_type3_packet(CP_SET_SHADER_BASES, 1);
*cmds++ = adreno_encode_istore_size(adreno_dev)
| adreno_dev->pix_shader_start;
cmds = program_shader(cmds, 0, gmem2sys_vtx_pgm, GMEM2SYS_VTX_PGM_LEN);
cmds =
program_shader(cmds, 1, gmem2sys_frag_pgm, GMEM2SYS_FRAG_PGM_LEN);
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_SQ_PROGRAM_CNTL);
if (adreno_is_a22x(adreno_dev))
*cmds++ = 0x10018001;
else
*cmds++ = 0x10010001;
*cmds++ = 0x00000008;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_CL_VTE_CNTL);
*cmds++ = 0x00000b00;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_RB_SURFACE_INFO);
*cmds++ = shadow->gmem_pitch;
BUG_ON(tmp_ctx.gmem_base & 0xFFF);
*cmds++ =
(shadow->
format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | tmp_ctx.gmem_base;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_DEPTHCONTROL);
if (adreno_is_a22x(adreno_dev))
*cmds++ = 0x08;
else
*cmds++ = 0;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_SU_SC_MODE_CNTL);
*cmds++ = 0x00080240;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_PA_SC_SCREEN_SCISSOR_TL);
*cmds++ = (0 << 16) | 0;
*cmds++ = (0x1fff << 16) | (0x1fff);
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL);
*cmds++ = (unsigned int)((1U << 31) | (0 << 16) | 0);
*cmds++ = (0x1fff << 16) | (0x1fff);
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_PA_CL_VPORT_ZSCALE);
*cmds++ = 0xbf800000;
*cmds++ = 0x0;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_COLOR_MASK);
*cmds++ = 0x0000000f;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_COLOR_DEST_MASK);
*cmds++ = 0xffffffff;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3);
*cmds++ = CP_REG(REG_SQ_WRAPPING_0);
*cmds++ = 0x00000000;
*cmds++ = 0x00000000;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 6);
*cmds++ = CP_REG(REG_RB_COPY_CONTROL);
*cmds++ = 0;
*cmds++ = addr & 0xfffff000;
*cmds++ = shadow->pitch >> 5;
*cmds++ = 0x0003c008 |
(shadow->format << RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT);
BUG_ON(offset & 0xfffff000);
*cmds++ = offset;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_RB_MODECONTROL);
*cmds++ = 0x6;
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_PA_CL_CLIP_CNTL);
*cmds++ = 0x00010000;
if (adreno_is_a22x(adreno_dev)) {
*cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmds++ = CP_REG(REG_A220_RB_LRZ_VSC_CONTROL);
*cmds++ = 0x0000000;
*cmds++ = cp_type3_packet(CP_DRAW_INDX, 3);
*cmds++ = 0;
*cmds++ = 0x00004088;
*cmds++ = 3;
} else {
*cmds++ = cp_type3_packet(CP_DRAW_INDX, 2);
*cmds++ = 0;
*cmds++ = 0x00030088;
}
create_ib1(drawctxt, shadow->gmem_save, start, cmds);
return cmds;
}
