void __init prom_init(void) { PSYSTEM_PARAMETER_BLOCK pb = PROMBLOCK; romvec = ROMVECTOR; prom_argc = fw_arg0; _prom_argv = (LONG *) fw_arg1; _prom_envp = (LONG *) fw_arg2; if (pb->magic != 0x53435241) { prom_printf("Aieee, bad prom vector magic %08lx\n", pb->magic); while(1) ; } prom_init_cmdline(); prom_identify_arch(); printk(KERN_INFO "PROMLIB: ARC firmware Version %d Revision %d\n", pb->ver, pb->rev); prom_meminit(); #ifdef DEBUG_PROM_INIT prom_printf("Press a key to reboot\n"); prom_getchar(); ArcEnterInteractiveMode(); #endif }
int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) { unsigned long mem_size; unsigned long pcicr; prom_argc = argc; prom_argv = argv; prom_envp = envp; puts("ITE board running..."); mips_machgroup = MACH_GROUP_ITE; mips_machtype = MACH_QED_4N_S01B; /* ITE board name/number */ prom_init_cmdline(); mem_size = prom_get_memsize(); printk("Memory size: %dMB\n", (unsigned)mem_size); mem_size <<= 20; /* MB */ /* * make the entire physical memory visible to pci bus masters */ IT_READ(IT_MC_PCICR, pcicr); pcicr &= ~0x1f; pcicr |= (mem_size - 1) >> 22; IT_WRITE(IT_MC_PCICR, pcicr); it8172_init_ram_resource(mem_size); add_memory_region(0, mem_size, BOOT_MEM_RAM); return 0; }
void __init prom_init(void) { int argc = fw_arg0; u32 *argv = (u32 *)CKSEG0ADDR(fw_arg1); int i; char console_string[40]; print_board_type(); kerSysEarlyFlashInit(); prom_init_cmdline(); strcat(arcs_cmdline, " "); for (i = 1; i < argc; i++) { strcat(arcs_cmdline, (char *)CKSEG0ADDR(argv[i])); if (i < (argc - 1)) strcat(arcs_cmdline, " "); } if(!strstr(arcs_cmdline, "console=ttyS")) { sprintf(console_string, " console=ttyS0,%d%c%c%c", 115200, 'n', '8', '\0'); strcat(arcs_cmdline, console_string); prom_printf("Config serial console:%s\n", console_string); } retrieve_boot_loader_parameters(); }
int __init prom_init(int argc, char **argv, char **envp) { prom_argc = argc; prom_argv = argv; prom_envp = envp; mips_display_message("LINUX"); /* * Setup the North bridge to do Master byte-lane swapping when * running in bigendian. */ #if defined(__MIPSEL__) GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | GT_PCI0_CMD_SBYTESWAP_BIT); #else GT_WRITE(GT_PCI0_CMD_OFS, 0); #endif #if defined(CONFIG_MIPS_MALTA) set_io_port_base(MALTA_PORT_BASE); #else set_io_port_base(KSEG1); #endif setup_prom_printf(0); prom_printf("\nLINUX started...\n"); prom_init_cmdline(); prom_meminit(); return 0; }
void __init prom_init(void) { #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG _loongson_addrwincfg_base = (unsigned long) ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE); #endif prom_init_cmdline(); prom_init_env(); /* init base address of io space */ set_io_port_base((unsigned long) ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); #ifdef CONFIG_NUMA prom_init_numa_memory(); #else prom_init_memory(); #endif /*init the uart base address */ prom_init_uart_base(); register_smp_ops(&loongson3_smp_ops); board_nmi_handler_setup = mips_nmi_setup; }
void __init prom_init(void) { prom_init_cfe(); prom_init_console(); prom_init_cmdline(); prom_init_mem(); }
int __init prom_init(int argc, char **argv, unsigned long magic, int *prom_vec) { extern void dec_machine_halt(void); /* Determine which PROM's we have (and therefore which machine we're on!) */ which_prom(magic, prom_vec); if (magic == REX_PROM_MAGIC) rex_clear_cache(); /* Were we compiled with the right CPU option? */ #if defined(CONFIG_CPU_R3000) if ((mips_cputype == CPU_R4000SC) || (mips_cputype == CPU_R4400SC)) { prom_printf("Sorry, this kernel is compiled for the wrong CPU type!\n"); prom_printf("Please recompile with \"CONFIG_CPU_R4x00 = y\"\n"); dec_machine_halt(); } #endif #if defined(CONFIG_CPU_R4x00) if ((mips_cputype == CPU_R3000) || (mips_cputype == CPU_R3000A)) { prom_printf("Sorry, this kernel is compiled for the wrong CPU type!\n"); prom_printf("Please recompile with \"CONFIG_CPU_R3000 = y\"\n"); dec_machine_halt(); } #endif prom_meminit(magic); prom_identify_arch(magic); prom_init_cmdline(argc, argv, magic); return 0; }
void __init prom_init(void) { unsigned char *memsize_str; unsigned long memsize; prom_argc = fw_arg0; prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; mips_machgroup = MACH_GROUP_ALCHEMY; /* Set the platform # */ #if defined (CONFIG_MIPS_DB1550) mips_machtype = MACH_DB1550; #elif defined (CONFIG_MIPS_DB1500) mips_machtype = MACH_DB1500; #elif defined (CONFIG_MIPS_DB1100) mips_machtype = MACH_DB1100; #else mips_machtype = MACH_DB1000; #endif prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str) memsize = 0x04000000; else memsize = simple_strtol(memsize_str, NULL, 0); add_memory_region(0, memsize, BOOT_MEM_RAM); }
void __init prom_init(void) { set_io_port_base(0xbfd00000); pr_info("\nLINUX started...\n"); prom_init_cmdline(); prom_meminit(); }
void prom_init(void) { set_io_port_base(0xbfd00000); prom_printf("\nLINUX started...\n"); prom_init_cmdline(); prom_meminit(); }
void __init prom_init(void) { prom_init_cmdline((int)fw_arg0, (char **)fw_arg1); mips_machtype = MACH_XBURST; #ifdef CONFIG_SMP register_smp_ops(&jzsoc_smp_ops); #endif }
void __init prom_init(void) { int argc; char **argv; prom_soc_init(&soc_info); pr_info("SoC Type: %s\n", get_system_type()); prom_init_cmdline(argc, argv); }
void __init prom_init(void) { prom_argc = fw_arg0; prom_argv = (char **)fw_arg1; prom_envp = (char **)fw_arg2; prom_init_cmdline(); memsize = env_or_default("memsize", DEFAULT_MEMSIZE); highmemsize = env_or_default("highmemsize", 0x0); }
void __init prom_init(void) { #ifdef CONFIG_TOSHIBA_JMR3927 /* CCFG */ if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) puts("Warning: TX3927 TLB off\n"); #endif prom_init_cmdline(); add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); }
void __init prom_init(void) { set_io_port_base(KSEG1); pr_info("\nLINUX started...\n"); prom_init_cmdline(); prom_meminit(); #ifdef CONFIG_SMP register_smp_ops(&z48soc_smp_ops); #endif }
void __init prom_init(void) { unsigned long memsize; prom_argc = fw_arg0; prom_argv = (char **)fw_arg1; prom_envp = (char **)fw_arg2; prom_init_cmdline(); memsize = env_or_default("memsize", 0x02000000); add_memory_region(0, memsize, BOOT_MEM_RAM); }
void __init prom_init(void) { struct clk *clk; ltq_soc_detect(&soc_info); clk_init(); clk = clk_get(0, "cpu"); snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d", soc_info.name, soc_info.rev); clk_put(clk); soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; pr_info("SoC: %s\n", soc_info.sys_type); prom_init_cmdline(); }
void __init prom_init(void) { extern void ATTRIB_NORET dec_machine_halt(void); static char cpu_msg[] __initdata = "Sorry, this kernel is compiled for a wrong CPU type!\n"; s32 argc = fw_arg0; s32 *argv = (void *)fw_arg1; u32 magic = fw_arg2; s32 *prom_vec = (void *)fw_arg3; /* * Determine which PROM we have * (and therefore which machine we're on!) */ which_prom(magic, prom_vec); if (prom_is_rex(magic)) rex_clear_cache(); /* Register the early console. */ register_prom_console(); /* Were we compiled with the right CPU option? */ #if defined(CONFIG_CPU_R3000) if ((current_cpu_data.cputype == CPU_R4000SC) || (current_cpu_data.cputype == CPU_R4400SC)) { static char r4k_msg[] __initdata = "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n"; printk(cpu_msg); printk(r4k_msg); dec_machine_halt(); } #endif #if defined(CONFIG_CPU_R4X00) if ((current_cpu_data.cputype == CPU_R3000) || (current_cpu_data.cputype == CPU_R3000A)) { static char r3k_msg[] __initdata = "Please recompile with \"CONFIG_CPU_R3000 = y\".\n"; printk(cpu_msg); printk(r3k_msg); dec_machine_halt(); } #endif prom_meminit(magic); prom_identify_arch(magic); prom_init_cmdline(argc, argv, magic); }
void __init prom_init(void) { extern int tx4938_get_mem_size(void); int msize; #ifndef CONFIG_TX4938_NAND_BOOT prom_init_cmdline(); #endif mips_machgroup = MACH_GROUP_TOSHIBA; mips_machtype = MACH_TOSHIBA_RBTX4938; msize = tx4938_get_mem_size(); add_memory_region(0, msize << 20, BOOT_MEM_RAM); return; }
void __init prom_init(void) { /* call the soc specific detetcion code and get it to fill soc_info */ ltq_soc_detect(&soc_info); snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s", soc_info.name, soc_info.rev_type); soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; pr_info("SoC: %s\n", soc_info.sys_type); prom_init_cmdline(); #if defined(CONFIG_MIPS_MT_SMP) if (register_vsmp_smp_ops()) panic("failed to register_vsmp_smp_ops()"); #endif }
void __init prom_init(void) { ltq_soc_detect(&soc_info); clk_init(); snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s", soc_info.name, soc_info.rev_type); soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; pr_info("SoC: %s\n", soc_info.sys_type); prom_init_cmdline(); #if defined(CONFIG_MIPS_MT_SMP) if (register_vsmp_smp_ops()) panic("failed to register_vsmp_smp_ops()"); #endif }
void __init prom_init(void) { unsigned long memsize; prom_argc = (int) fw_arg0; prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; prom_init_cmdline(); mips_machgroup = MACH_GROUP_PHILIPS; mips_machtype = MACH_PHILIPS_STB810; memsize = 0x08000000; /* Trimedia uses memory above */ add_memory_region(0, memsize, BOOT_MEM_RAM); }
void __init prom_init(void) { unsigned char *memsize_str; unsigned long memsize; prom_argc = (int)fw_arg0; prom_argv = (char **)fw_arg1; prom_envp = (char **)fw_arg2; prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str || kstrtoul(memsize_str, 0, &memsize)) memsize = 64 << 20; /* all devboards have at least 64MB RAM */ add_memory_region(0, memsize, BOOT_MEM_RAM); }
void __init prom_init(void) { unsigned char *memsize_str; unsigned long memsize; prom_argc = (int)fw_arg0; prom_argv = (char **)fw_arg1; prom_envp = (char **)fw_arg2; prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize)) memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE; add_memory_region(0, memsize, BOOT_MEM_RAM); }
void __init prom_init(void) { unsigned char *memsize_str; unsigned long memsize; prom_argc = fw_arg0; prom_argv = (char **)fw_arg1; prom_envp = (char **)fw_arg2; prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str || kstrtoul(memsize_str, 0, &memsize)) memsize = 0x04000000; add_memory_region(0, memsize, BOOT_MEM_RAM); }
void __init prom_init(int argc, char **argv, char **envp, int *prom_vec) { struct linux_promblock *pb; romvec = ROMVECTOR; pb = sgi_pblock = PROMBLOCK; prom_argc = argc; prom_argv = argv; prom_envp = envp; #if 0 /* arc_printf should not use prom_printf as soon as we free * the prom buffers - This horribly breaks on Indys with framebuffer * as it simply stops after initialising swap - On the Indigo2 serial * console you will get A LOT illegal instructions - Only enable * this for early init crashes - This also brings up artefacts of * printing everything twice on serial console and on GFX Console * this has the effect of having the prom printing everything * in the small rectangle and the kernel printing around. */ arc_setup_console(); #endif if (pb->magic != 0x53435241) { prom_printf("Aieee, bad prom vector magic %08lx\n", pb->magic); while(1) ; } prom_init_cmdline(); prom_vers = pb->ver; prom_rev = pb->rev; prom_identify_arch(); printk("PROMLIB: ARC firmware Version %d Revision %d\n", prom_vers, prom_rev); prom_meminit(); #ifdef DEBUG_PROM_INIT { prom_printf("Press a key to reboot\n"); (void) prom_getchar(); romvec->imode(); } #endif }
void __init prom_init(int argc, char **argv, char **envp, int *prom_vec) { volatile unsigned char *uart; char ppbuf[8]; prom_argc = argc; prom_argv = argv; prom_envp = envp; mips_machgroup = MACH_GROUP_GALILEO; mips_machtype = MACH_EV96100; prom_init_cmdline(); /* 32 MB upgradable */ add_memory_region(0, 32 << 20, BOOT_MEM_RAM); }
void __init prom_init(void) { unsigned char *memsize_str; unsigned long memsize; prom_argc = (int)fw_arg0; prom_argv = (char **)fw_arg1; prom_envp = (char **)fw_arg2; prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str) memsize = 0x08000000; else memsize = strict_strtol(memsize_str, 0, NULL); add_memory_region(0, memsize, BOOT_MEM_RAM); }
void __init prom_init(void) { /* init base address of io space */ set_io_port_base((unsigned long) ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG _loongson_addrwincfg_base = (unsigned long) ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE); #endif prom_init_cmdline(); prom_init_env(); prom_init_memory(); /*init the uart base address */ prom_init_uart_base(); }
void __init prom_init(void) { unsigned char *memsize_str; unsigned long memsize; prom_argc = (int) fw_arg0; prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str) { memsize = 0x04000000; } else { memsize = simple_strtol(memsize_str, NULL, 0); } add_memory_region(0, memsize, BOOT_MEM_RAM); }