/* Entry from cache-as-ram.inc. */
void * asmlinkage romstage_main(unsigned long bist,
uint32_t tsc_low, uint32_t tsc_hi)
{
struct romstage_params rp = {
.bist = bist,
.mrc_params = NULL,
};
/* Save initial timestamp from bootblock. */
timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low);
/* Save romstage begin */
timestamp_add_now(TS_START_ROMSTAGE);
program_base_addresses();
tco_disable();
byt_config_com1_and_enable();
console_init();
spi_init();
set_max_freq();
punit_init();
gfx_init();
#if CONFIG_EC_GOOGLE_CHROMEEC
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
#endif
/* Call into mainboard. */
mainboard_romstage_entry(&rp);
return setup_stack_and_mttrs();
}
/* Entry from cache-as-ram.inc. */
void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low,
uint32_t tsc_hi)
{
struct romstage_params rp = {
.bist = bist,
.mrc_params = NULL,
};
/* Save initial timestamp from bootblock. */
timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low);
/* Save romstage begin */
timestamp_add_now(TS_START_ROMSTAGE);
program_base_addresses();
tco_disable();
byt_config_com1_and_enable();
console_init();
spi_init();
set_max_freq();
punit_init();
gfx_init();
/* Call into mainboard. */
mainboard_romstage_entry(&rp);
platform_enter_postcar();
/* We don't return here */
return NULL;
}
asmlinkage void car_stage_entry(void)
{
struct postcar_frame pcf;
uintptr_t top_of_ram;
bool s3wake;
struct chipset_power_state *ps = car_get_var_ptr(&power_state);
void *smm_base;
size_t smm_size, var_size;
const void *new_var_data;
uintptr_t tseg_base;
timestamp_add_now(TS_START_ROMSTAGE);
soc_early_romstage_init();
disable_watchdog();
console_init();
s3wake = fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake);
if (punit_init())
set_max_freq();
else
printk(BIOS_DEBUG, "Punit failed to initialize properly\n");
/* Stash variable MRC data and let cache system update it later */
new_var_data = fsp_find_extension_hob_by_guid(hob_variable_guid,
&var_size);
if (new_var_data)
mrc_cache_stash_vardata(new_var_data, var_size,
car_get_var(fsp_version));
else
printk(BIOS_ERR, "Failed to determine variable data\n");
if (postcar_frame_init(&pcf, 1*KiB))
die("Unable to initialize postcar frame.\n");
mainboard_save_dimm_info();
/*
* We need to make sure ramstage will be run cached. At this point exact
* location of ramstage in cbmem is not known. Instruct postcar to cache
* 16 megs under cbmem top which is a safe bet to cover ramstage.
*/
top_of_ram = (uintptr_t) cbmem_top();
/* cbmem_top() needs to be at least 16 MiB aligned */
assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram);
postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK);
/* Cache the memory-mapped boot media. */
if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
MTRR_TYPE_WRPROT);
/*
* Cache the TSEG region at the top of ram. This region is
* not restricted to SMM mode until SMM has been relocated.
* By setting the region to cacheable it provides faster access
* when relocating the SMM handler as well as using the TSEG
* region for other purposes.
*/
smm_region(&smm_base, &smm_size);
tseg_base = (uintptr_t)smm_base;
postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
run_postcar_phase(&pcf);
}