PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem, hwaddr base, BlockBackend *blk, qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) { DeviceState *dev, *carddev; SysBusDevice *sbd; PXA2xxMMCIState *s; Error *err = NULL; dev = qdev_create(NULL, TYPE_PXA2XX_MMCI); s = PXA2XX_MMCI(dev); sbd = SYS_BUS_DEVICE(dev); sysbus_mmio_map(sbd, 0, base); sysbus_connect_irq(sbd, 0, irq); qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma); qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma); /* Create and plug in the sd card */ carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); qdev_prop_set_drive(carddev, "drive", blk, &err); if (err) { error_report("failed to init SD card: %s", error_get_pretty(err)); return NULL; } object_property_set_bool(OBJECT(carddev), true, "realized", &err); if (err) { error_report("failed to init SD card: %s", error_get_pretty(err)); return NULL; } return s; }
static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { PL080State *dma = opaque; int i = dma - &mms->dma[0]; SysBusDevice *s; char *mscname = g_strdup_printf("%s-msc", name); TZMSC *msc = &mms->msc[i]; DeviceState *iotkitdev = DEVICE(&mms->iotkit); MemoryRegion *msc_upstream; MemoryRegion *msc_downstream; /* * Each DMA device is a PL081 whose transaction master interface * is guarded by a Master Security Controller. The downstream end of * the MSC connects to the IoTKit AHB Slave Expansion port, so the * DMA devices can see all devices and memory that the CPU does. */ sysbus_init_child_obj(OBJECT(mms), mscname, msc, sizeof(*msc), TYPE_TZ_MSC); msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); object_property_set_link(OBJECT(msc), OBJECT(msc_downstream), "downstream", &error_fatal); object_property_set_link(OBJECT(msc), OBJECT(mms), "idau", &error_fatal); object_property_set_bool(OBJECT(msc), true, "realized", &error_fatal); qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, qdev_get_gpio_in_named(iotkitdev, "mscexp_status", i)); qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i, qdev_get_gpio_in_named(DEVICE(msc), "irq_clear", 0)); qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i, qdev_get_gpio_in_named(DEVICE(msc), "cfg_nonsec", 0)); qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), ARRAY_SIZE(mms->ppc) + i, qdev_get_gpio_in_named(DEVICE(msc), "cfg_sec_resp", 0)); msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); sysbus_init_child_obj(OBJECT(mms), name, dma, sizeof(*dma), TYPE_PL081); object_property_set_link(OBJECT(dma), OBJECT(msc_upstream), "downstream", &error_fatal); object_property_set_bool(OBJECT(dma), true, "realized", &error_fatal); s = SYS_BUS_DEVICE(dma); /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3)); sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3)); sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3)); g_free(mscname); return sysbus_mmio_get_region(s, 0); }
static inline XilinxPCIEHost * xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr, hwaddr cfg_base, uint64_t cfg_size, hwaddr mmio_base, uint64_t mmio_size, qemu_irq irq, bool link_up) { DeviceState *dev; MemoryRegion *cfg, *mmio; dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST); qdev_prop_set_uint32(dev, "bus_nr", bus_nr); qdev_prop_set_uint64(dev, "cfg_base", cfg_base); qdev_prop_set_uint64(dev, "cfg_size", cfg_size); qdev_prop_set_uint64(dev, "mmio_base", mmio_base); qdev_prop_set_uint64(dev, "mmio_size", mmio_size); qdev_prop_set_bit(dev, "link_up", link_up); qdev_init_nofail(dev); cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0); mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0); qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq); return XILINX_PCIE_HOST(dev); }
void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq) { SysBusDeviceClass *sbd = SYS_BUS_DEVICE_GET_CLASS(dev); qdev_connect_gpio_out_named(DEVICE(dev), SYSBUS_DEVICE_GPIO_IRQ, n, irq); if (sbd->connect_irq_notifier) { sbd->connect_irq_notifier(dev, irq); } }
void nios2_iic_create(Nios2CPU *cpu) { DeviceState *dev; dev = qdev_create(NULL, "altera,iic"); object_property_add_const_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort); qdev_init_nofail(dev); cpu->env.pic_state = dev; qdev_connect_gpio_out_named(dev, "irq", 0, qdev_get_gpio_in(DEVICE(cpu), 0)); }
static void fdt_init_all_irqs(FDTMachineInfo *fdti) { while (fdti->irqs) { FDTIRQConnection *first = fdti->irqs; qemu_irq sink = first->irq; bool (*merge_fn)(bool *, int) = first->merge_fn; int num_sources = 0; FDTIRQConnection *irq; for (irq = first; irq; irq = irq->next) { if (irq->irq == sink) { /* Same sink */ num_sources++; } } if (num_sources > 1) { QEMUIRQSharedState *s = g_malloc0(sizeof *s); s->sink = sink; s->merge_fn = merge_fn; qemu_irq *sources = qemu_allocate_irqs(qemu_irq_shared_handler, s, num_sources); for (irq = first; irq; irq = irq->next) { if (irq->irq == sink) { char *shared_irq_name = g_strdup_printf("shared-irq-%p", *sources); if (irq->merge_fn != merge_fn) { fprintf(stderr, "ERROR: inconsistent IRQ merge fns\n"); exit(1); } object_property_add_child(OBJECT(irq->dev), shared_irq_name, OBJECT(*sources), &error_abort); g_free(shared_irq_name); irq->irq = *(sources++); s->num++; } } } DB_PRINT(0, "%s: connected to %s irq line %d (%s)\n", first->sink_info ? first->sink_info : "", object_get_canonical_path(OBJECT(first->dev)), first->i, first->name ? first->name : ""); qdev_connect_gpio_out_named(DEVICE(first->dev), first->name, first->i, first->irq); fdti->irqs = first->next; g_free(first); } }
static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { TZMPC *mpc = opaque; int i = mpc - &mms->ssram_mpc[0]; MemoryRegion *ssram = &mms->ssram[i]; MemoryRegion *upstream; char *mpcname = g_strdup_printf("%s-mpc", name); static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 }; static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 }; memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->ssram_mpc[0]), TYPE_TZ_MPC); object_property_set_link(OBJECT(mpc), OBJECT(ssram), "downstream", &error_fatal); object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal); /* Map the upstream end of the MPC into system memory */ upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); memory_region_add_subregion(get_system_memory(), rambase[i], upstream); /* and connect its interrupt to the IoTKit */ qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "mpcexp_status", i)); /* The first SSRAM is a special case as it has an alias; accesses to * the alias region at 0x00400000 must also go to the MPC upstream. */ if (i == 0) { make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000); } g_free(mpcname); /* Return the register interface MR for our caller to map behind the PPC */ return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); }
static void altera_iic_fdt_auto_parent(FDTGenericIntc *obj, Error **errp) { qdev_connect_gpio_out_named(DEVICE(obj), "irq", 0, qdev_get_gpio_in(DEVICE(first_cpu), 0)); }
/* PC hardware initialisation */ static void pc_q35_init(MachineState *machine) { PCMachineState *pcms = PC_MACHINE(machine); PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); Q35PCIHost *q35_host; PCIHostState *phb; PCIBus *host_bus; PCIDevice *lpc; DeviceState *lpc_dev; BusState *idebus[MAX_SATA_PORTS]; ISADevice *rtc_state; MemoryRegion *system_io = get_system_io(); MemoryRegion *pci_memory; MemoryRegion *rom_memory; MemoryRegion *ram_memory; GSIState *gsi_state; ISABus *isa_bus; qemu_irq *i8259; int i; ICH9LPCState *ich9_lpc; PCIDevice *ahci; ram_addr_t lowmem; DriveInfo *hd[MAX_SATA_PORTS]; MachineClass *mc = MACHINE_GET_CLASS(machine); /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping * also known as MMCFG). * If it doesn't, we need to split it in chunks below and above 4G. * In any case, try to make sure that guest addresses aligned at * 1G boundaries get mapped to host addresses aligned at 1G boundaries. */ if (machine->ram_size >= 0xb0000000) { lowmem = 0x80000000; } else { lowmem = 0xb0000000; } /* Handle the machine opt max-ram-below-4g. It is basically doing * min(qemu limit, user limit). */ if (!pcms->max_ram_below_4g) { pcms->max_ram_below_4g = 1ULL << 32; /* default: 4G */; } if (lowmem > pcms->max_ram_below_4g) { lowmem = pcms->max_ram_below_4g; if (machine->ram_size - lowmem > lowmem && lowmem & ((1ULL << 30) - 1)) { error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64 ") not a multiple of 1G; possible bad performance.", pcms->max_ram_below_4g); } } if (machine->ram_size >= lowmem) { pcms->above_4g_mem_size = machine->ram_size - lowmem; pcms->below_4g_mem_size = lowmem; } else { pcms->above_4g_mem_size = 0; pcms->below_4g_mem_size = machine->ram_size; } if (xen_enabled()) { xen_hvm_init(pcms, &ram_memory); } pc_cpus_init(pcms); kvmclock_create(); /* pci enabled */ if (pcmc->pci_enabled) { pci_memory = g_new(MemoryRegion, 1); memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); rom_memory = pci_memory; } else { pci_memory = NULL; rom_memory = get_system_memory(); } pc_guest_info_init(pcms); if (pcmc->smbios_defaults) { /* These values are guest ABI, do not change */ smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", mc->name, pcmc->smbios_legacy_mode, pcmc->smbios_uuid_encoded, SMBIOS_ENTRY_POINT_21); } /* allocate ram and load rom/bios */ if (!xen_enabled()) { pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory); } /* irq lines */ gsi_state = g_malloc0(sizeof(*gsi_state)); if (kvm_ioapic_in_kernel()) { kvm_pc_setup_irq_routing(pcmc->pci_enabled); pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, GSI_NUM_PINS); } else { pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); } /* create pci host bus */ q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory), MCH_HOST_PROP_RAM_MEM, NULL); object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory), MCH_HOST_PROP_PCI_MEM, NULL); object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()), MCH_HOST_PROP_SYSTEM_MEM, NULL); object_property_set_link(OBJECT(q35_host), OBJECT(system_io), MCH_HOST_PROP_IO_MEM, NULL); object_property_set_int(OBJECT(q35_host), pcms->below_4g_mem_size, PCI_HOST_BELOW_4G_MEM_SIZE, NULL); object_property_set_int(OBJECT(q35_host), pcms->above_4g_mem_size, PCI_HOST_ABOVE_4G_MEM_SIZE, NULL); /* pci */ qdev_init_nofail(DEVICE(q35_host)); phb = PCI_HOST_BRIDGE(q35_host); host_bus = phb->bus; /* create ISA bus */ lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true, TYPE_ICH9_LPC_DEVICE); object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, TYPE_HOTPLUG_HANDLER, (Object **)&pcms->acpi_dev, object_property_allow_set_link, OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); object_property_set_link(OBJECT(machine), OBJECT(lpc), PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); ich9_lpc = ICH9_LPC_DEVICE(lpc); lpc_dev = DEVICE(lpc); for (i = 0; i < GSI_NUM_PINS; i++) { qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, pcms->gsi[i]); } pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, ICH9_LPC_NB_PIRQS); pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); isa_bus = ich9_lpc->isa_bus; if (kvm_pic_in_kernel()) { i8259 = kvm_i8259_init(isa_bus); } else if (xen_enabled()) { i8259 = xen_interrupt_controller_init(); } else { i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq()); } for (i = 0; i < ISA_NUM_IRQS; i++) { gsi_state->i8259_irq[i] = i8259[i]; } g_free(i8259); if (pcmc->pci_enabled) { ioapic_init_gsi(gsi_state, "q35"); } pc_register_ferr_irq(pcms->gsi[13]); assert(pcms->vmport != ON_OFF_AUTO__MAX); if (pcms->vmport == ON_OFF_AUTO_AUTO) { pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; } /* init basic PC hardware */ pc_basic_device_init(isa_bus, pcms->gsi, &rtc_state, !mc->no_floppy, (pcms->vmport != ON_OFF_AUTO_ON), 0xff0104); /* connect pm stuff to lpc */ ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms)); /* ahci and SATA device, for q35 1 ahci controller is built-in */ ahci = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_SATA1_DEV, ICH9_SATA1_FUNC), true, "ich9-ahci"); idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports); ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports); ahci_ide_create_devs(ahci, hd); if (machine_usb(machine)) { /* Should we create 6 UHCI according to ich9 spec? */ ehci_create_ich9_with_companions(host_bus, 0x1d); } /* TODO: Populate SPD eeprom data. */ smbus_eeprom_init(ich9_smb_init(host_bus, PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 0xb100), 8, NULL, 0); pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); /* the rest devices to which pci devfn is automatically assigned */ pc_vga_init(isa_bus, host_bus); pc_nic_init(isa_bus, host_bus); if (pcmc->pci_enabled) { pc_pci_device_init(host_bus); } if (pcms->acpi_nvdimm_state.is_enabled) { nvdimm_init_acpi_state(&pcms->acpi_nvdimm_state, system_io, pcms->fw_cfg, OBJECT(pcms)); } }
static void sun4uv_init(MemoryRegion *address_space_mem, MachineState *machine, const struct hwdef *hwdef) { SPARCCPU *cpu; Nvram *nvram; unsigned int i; uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; SabreState *sabre; PCIBus *pci_bus, *pci_busA, *pci_busB; PCIDevice *ebus, *pci_dev; SysBusDevice *s; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; DeviceState *iommu, *dev; FWCfgState *fw_cfg; NICInfo *nd; MACAddr macaddr; bool onboard_nic; /* init CPUs */ cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); /* IOMMU */ iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU); qdev_init_nofail(iommu); /* set up devices */ ram_init(0, machine->ram_size); prom_init(hwdef->prom_addr, bios_name); /* Init sabre (PCI host bridge) */ sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE)); qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu", &error_abort); qdev_init_nofail(DEVICE(sabre)); /* Wire up PCI interrupts to CPU */ for (i = 0; i < IVEC_MAX; i++) { qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i, qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); } pci_bus = PCI_HOST_BRIDGE(sabre)->bus; pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA); pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB); /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is reserved (leaving no slots free after on-board devices) however slots 0-3 are free on busB */ pci_bus->slot_reserved_mask = 0xfffffffc; pci_busA->slot_reserved_mask = 0xfffffff1; pci_busB->slot_reserved_mask = 0xfffffff0; ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS); qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", hwdef->console_serial_base); qdev_init_nofail(DEVICE(ebus)); /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */ qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ)); qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ)); qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ)); qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ)); qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ)); pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); memset(&macaddr, 0, sizeof(MACAddr)); onboard_nic = false; for (i = 0; i < nb_nics; i++) { nd = &nd_table[i]; if (!nd->model || strcmp(nd->model, "sunhme") == 0) { if (!onboard_nic) { pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), true, "sunhme"); memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); onboard_nic = true; } else { pci_dev = pci_create(pci_busB, -1, "sunhme"); } } else { pci_dev = pci_create(pci_busB, -1, nd->model); } dev = &pci_dev->qdev; qdev_set_nic_properties(dev, nd); qdev_init_nofail(dev); } /* If we don't have an onboard NIC, grab a default MAC address so that * we have a valid machine id */ if (!onboard_nic) { qemu_macaddr_default_if_unset(&macaddr); } ide_drive_get(hd, ARRAY_SIZE(hd)); pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); qdev_init_nofail(&pci_dev->qdev); pci_ide_create_devs(pci_dev, hd); /* Map NVRAM into I/O (ebus) space */ nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); s = SYS_BUS_DEVICE(nvram); memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, sysbus_mmio_get_region(s, 0)); initrd_size = 0; initrd_addr = 0; kernel_size = sun4u_load_kernel(machine->kernel_filename, machine->initrd_filename, ram_size, &initrd_size, &initrd_addr, &kernel_addr, &kernel_entry); sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, machine->boot_order, kernel_addr, kernel_size, machine->kernel_cmdline, initrd_addr, initrd_size, /* XXX: need an option to load a NVRAM image */ 0, graphic_width, graphic_height, graphic_depth, (uint8_t *)&macaddr); dev = qdev_create(NULL, TYPE_FW_CFG_IO); qdev_prop_set_bit(dev, "dma_enabled", false); object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); qdev_init_nofail(dev); memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, &FW_CFG_IO(dev)->comb_iomem); fw_cfg = FW_CFG(dev); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); if (machine->kernel_cmdline) { fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(machine->kernel_cmdline) + 1); fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); } else { fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); } fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); }
void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq) { qdev_connect_gpio_out_named(DEVICE(dev), SYSBUS_DEVICE_GPIO_IRQ, n, irq); }
void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out) { qdev_connect_gpio_out_named(DEVICE(dev), I8042_A20_LINE, 0, *a20_out); }
static void mps2tz_common_init(MachineState *machine) { MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); MachineClass *mc = MACHINE_GET_CLASS(machine); MemoryRegion *system_memory = get_system_memory(); DeviceState *iotkitdev; DeviceState *dev_splitter; int i; if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { error_report("This board can only be used with CPU %s", mc->default_cpu_type); exit(1); } sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit, sizeof(mms->iotkit), TYPE_IOTKIT); iotkitdev = DEVICE(&mms->iotkit); object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), "memory", &error_abort); qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", 92); qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); object_property_set_bool(OBJECT(&mms->iotkit), true, "realized", &error_fatal); /* The sec_resp_cfg output from the IoTKit must be split into multiple * lines, one for each of the PPCs we create here. */ object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter), TYPE_SPLIT_IRQ); object_property_add_child(OBJECT(machine), "sec-resp-splitter", OBJECT(&mms->sec_resp_splitter), &error_abort); object_property_set_int(OBJECT(&mms->sec_resp_splitter), 5, "num-lines", &error_fatal); object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true, "realized", &error_fatal); dev_splitter = DEVICE(&mms->sec_resp_splitter); qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, qdev_get_gpio_in(dev_splitter, 0)); /* The IoTKit sets up much of the memory layout, including * the aliases between secure and non-secure regions in the * address space. The FPGA itself contains: * * 0x00000000..0x003fffff SSRAM1 * 0x00400000..0x007fffff alias of SSRAM1 * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices * 0x80000000..0x80ffffff 16MB PSRAM */ /* The FPGA images have an odd combination of different RAMs, * because in hardware they are different implementations and * connected to different buses, giving varying performance/size * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily * call the 16MB our "system memory", as it's the largest lump. */ memory_region_allocate_system_memory(&mms->psram, NULL, "mps.ram", 0x01000000); memory_region_add_subregion(system_memory, 0x80000000, &mms->psram); /* The overflow IRQs for all UARTs are ORed together. * Tx, Rx and "combined" IRQs are sent to the NVIC separately. * Create the OR gate for this. */ object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate), TYPE_OR_IRQ); object_property_add_child(OBJECT(mms), "uart-irq-orgate", OBJECT(&mms->uart_irq_orgate), &error_abort); object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines", &error_fatal); object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true, "realized", &error_fatal); qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 15)); /* Most of the devices in the FPGA are behind Peripheral Protection * Controllers. The required order for initializing things is: * + initialize the PPC * + initialize, configure and realize downstream devices * + connect downstream device MemoryRegions to the PPC * + realize the PPC * + map the PPC's MemoryRegions to the places in the address map * where the downstream devices should appear * + wire up the PPC's control lines to the IoTKit object */ const PPCInfo ppcs[] = { { .name = "apb_ppcexp0", .ports = { { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 }, { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 }, { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 }, }, }, { .name = "apb_ppcexp1",
static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) { MSF2State *s = MSF2_SOC(dev_soc); DeviceState *dev, *armv7m; SysBusDevice *busdev; Error *err = NULL; int i; MemoryRegion *system_memory = get_system_memory(); MemoryRegion *nvm = g_new(MemoryRegion, 1); MemoryRegion *nvm_alias = g_new(MemoryRegion, 1); MemoryRegion *sram = g_new(MemoryRegion, 1); memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size, &error_fatal); /* * On power-on, the eNVM region 0x60000000 is automatically * remapped to the Cortex-M3 processor executable region * start address (0x0). We do not support remapping other eNVM, * eSRAM and DDR regions by guest(via Sysreg) currently. */ memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM", nvm, 0, s->envm_size); memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm); memory_region_add_subregion(system_memory, 0, nvm_alias); memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size, &error_fatal); memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 81); qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), "memory", &error_abort); object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } if (!s->m3clk) { error_setg(errp, "Invalid m3clk value"); error_append_hint(errp, "m3clk can not be zero\n"); return; } qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0, qemu_allocate_irq(&do_sys_reset, NULL, 0)); system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk; for (i = 0; i < MSF2_NUM_UARTS; i++) { if (serial_hd(i)) { serial_mm_init(get_system_memory(), uart_addr[i], 2, qdev_get_gpio_in(armv7m, uart_irq[i]), 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN); } } dev = DEVICE(&s->timer); /* APB0 clock is the timer input clock */ qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div); object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } busdev = SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[0])); sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(armv7m, timer_irq[1])); dev = DEVICE(&s->sysreg); qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div); qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div); object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } busdev = SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE); for (i = 0; i < MSF2_NUM_SPIS; i++) { gchar *bus_name; object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, qdev_get_gpio_in(armv7m, spi_irq[i])); /* Alias controller SPI bus to the SoC itself */ bus_name = g_strdup_printf("spi%d", i); object_property_add_alias(OBJECT(s), bus_name, OBJECT(&s->spi[i]), "spi", &error_abort); g_free(bus_name); } /* Below devices are not modelled yet. */ create_unimplemented_device("i2c_0", 0x40002000, 0x1000); create_unimplemented_device("dma", 0x40003000, 0x1000); create_unimplemented_device("watchdog", 0x40005000, 0x1000); create_unimplemented_device("i2c_1", 0x40012000, 0x1000); create_unimplemented_device("gpio", 0x40013000, 0x1000); create_unimplemented_device("hs-dma", 0x40014000, 0x1000); create_unimplemented_device("can", 0x40015000, 0x1000); create_unimplemented_device("rtc", 0x40017000, 0x1000); create_unimplemented_device("apb_config", 0x40020000, 0x10000); create_unimplemented_device("emac", 0x40041000, 0x1000); create_unimplemented_device("usb", 0x40043000, 0x1000); }
static void bcm2836_realize(DeviceState *dev, Error **errp) { BCM2836State *s = BCM2836(dev); Object *obj; Error *err = NULL; int n; /* common peripherals from bcm2835 */ obj = OBJECT(dev); for (n = 0; n < BCM2836_NCPUS; n++) { object_initialize(&s->cpus[n], sizeof(s->cpus[n]), s->cpu_type); object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), &error_abort); } obj = object_property_get_link(OBJECT(dev), "ram", &err); if (obj == NULL) { error_setg(errp, "%s: required ram link not found: %s", __func__, error_get_pretty(err)); return; } object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj, &err); if (err) { error_propagate(errp, err); return; } object_property_set_bool(OBJECT(&s->peripherals), true, "realized", &err); if (err) { error_propagate(errp, err); return; } object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals), "sd-bus", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, BCM2836_PERI_BASE, 1); /* bcm2836 interrupt controller (and mailboxes, etc.) */ object_property_set_bool(OBJECT(&s->control), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, BCM2836_CONTROL_BASE); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); for (n = 0; n < BCM2836_NCPUS; n++) { /* Mirror bcm2836, which has clusterid set to 0xf * TODO: this should be converted to a property of ARM_CPU */ s->cpus[n].mp_affinity = 0xF00 | n; /* set periphbase/CBAR value for CPU-local registers */ object_property_set_int(OBJECT(&s->cpus[n]), BCM2836_PERI_BASE + MCORE_OFFSET, "reset-cbar", &err); if (err) { error_propagate(errp, err); return; } /* start powered off if not enabled */ object_property_set_bool(OBJECT(&s->cpus[n]), n >= s->enabled_cpus, "start-powered-off", &err); if (err) { error_propagate(errp, err); return; } object_property_set_bool(OBJECT(&s->cpus[n]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } /* Connect irq/fiq outputs from the interrupt controller. */ qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n, qdev_get_gpio_in(DEVICE(&s->cpus[n]), ARM_CPU_IRQ)); qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n, qdev_get_gpio_in(DEVICE(&s->cpus[n]), ARM_CPU_FIQ)); /* Connect timers from the CPU to the interrupt controller */ qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_PHYS, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n)); qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_VIRT, qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n)); qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_HYP, qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n)); qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_SEC, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)); } }