static void put_tlb(QEMUFile *f, void *pv, size_t size)
{
r4k_tlb_t *v = pv;
uint8_t asid = v->ASID;
uint16_t flags = ((v->EHINV << 15) |
(v->RI1 << 14) |
(v->RI0 << 13) |
(v->XI1 << 12) |
(v->XI0 << 11) |
(v->G << 10) |
(v->C0 << 7) |
(v->C1 << 4) |
(v->V0 << 3) |
(v->V1 << 2) |
(v->D0 << 1) |
(v->D1 << 0));
qemu_put_betls(f, &v->VPN);
qemu_put_be32s(f, &v->PageMask);
qemu_put_8s(f, &asid);
qemu_put_be16s(f, &flags);
qemu_put_be64s(f, &v->PFN[0]);
qemu_put_be64s(f, &v->PFN[1]);
}
static int put_tlb(QEMUFile *f, void *pv, size_t size,
const VMStateField *field, QJSON *vmdesc)
{
r4k_tlb_t *v = pv;
uint16_t asid = v->ASID;
uint16_t flags = ((v->EHINV << 15) |
(v->RI1 << 14) |
(v->RI0 << 13) |
(v->XI1 << 12) |
(v->XI0 << 11) |
(v->G << 10) |
(v->C0 << 7) |
(v->C1 << 4) |
(v->V0 << 3) |
(v->V1 << 2) |
(v->D0 << 1) |
(v->D1 << 0));
qemu_put_betls(f, &v->VPN);
qemu_put_be32s(f, &v->PageMask);
qemu_put_be16s(f, &asid);
qemu_put_be16s(f, &flags);
qemu_put_be64s(f, &v->PFN[0]);
qemu_put_be64s(f, &v->PFN[1]);
return 0;
}
static void save_tc(QEMUFile *f, TCState *tc)
{
int i;
/* Save active TC */
for(i = 0; i < 32; i++)
qemu_put_betls(f, &tc->gpr[i]);
qemu_put_betls(f, &tc->PC);
for(i = 0; i < MIPS_DSP_ACC; i++)
qemu_put_betls(f, &tc->HI[i]);
for(i = 0; i < MIPS_DSP_ACC; i++)
qemu_put_betls(f, &tc->LO[i]);
for(i = 0; i < MIPS_DSP_ACC; i++)
qemu_put_betls(f, &tc->ACX[i]);
qemu_put_betls(f, &tc->DSPControl);
qemu_put_sbe32s(f, &tc->CP0_TCStatus);
qemu_put_sbe32s(f, &tc->CP0_TCBind);
qemu_put_betls(f, &tc->CP0_TCHalt);
qemu_put_betls(f, &tc->CP0_TCContext);
qemu_put_betls(f, &tc->CP0_TCSchedule);
qemu_put_betls(f, &tc->CP0_TCScheFBack);
qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus);
}
void cpu_save(QEMUFile *f, void *opaque)
{
CPUMIPSState *env = opaque;
int i;
/* Save active TC */
save_tc(f, &env->active_tc);
/* Save active FPU */
save_fpu(f, &env->active_fpu);
/* Save MVP */
qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl);
qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0);
qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1);
/* Save TLB */
qemu_put_be32s(f, &env->tlb->nb_tlb);
for(i = 0; i < MIPS_TLB_MAX; i++) {
uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].G << 10) |
(env->tlb->mmu.r4k.tlb[i].C0 << 7) |
(env->tlb->mmu.r4k.tlb[i].C1 << 4) |
(env->tlb->mmu.r4k.tlb[i].V0 << 3) |
(env->tlb->mmu.r4k.tlb[i].V1 << 2) |
(env->tlb->mmu.r4k.tlb[i].D0 << 1) |
(env->tlb->mmu.r4k.tlb[i].D1 << 0));
uint8_t asid;
qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
asid = env->tlb->mmu.r4k.tlb[i].ASID;
qemu_put_8s(f, &asid);
qemu_put_be16s(f, &flags);
qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
}
/* Save CPU metastate */
qemu_put_be32s(f, &env->current_tc);
qemu_put_be32s(f, &env->current_fpu);
qemu_put_sbe32s(f, &env->error_code);
qemu_put_be32s(f, &env->hflags);
qemu_put_betls(f, &env->btarget);
i = env->bcond;
qemu_put_sbe32s(f, &i);
/* Save remaining CP1 registers */
qemu_put_sbe32s(f, &env->CP0_Index);
qemu_put_sbe32s(f, &env->CP0_Random);
qemu_put_sbe32s(f, &env->CP0_VPEControl);
qemu_put_sbe32s(f, &env->CP0_VPEConf0);
qemu_put_sbe32s(f, &env->CP0_VPEConf1);
qemu_put_betls(f, &env->CP0_YQMask);
qemu_put_betls(f, &env->CP0_VPESchedule);
qemu_put_betls(f, &env->CP0_VPEScheFBack);
qemu_put_sbe32s(f, &env->CP0_VPEOpt);
qemu_put_betls(f, &env->CP0_EntryLo0);
qemu_put_betls(f, &env->CP0_EntryLo1);
qemu_put_betls(f, &env->CP0_Context);
qemu_put_sbe32s(f, &env->CP0_PageMask);
qemu_put_sbe32s(f, &env->CP0_PageGrain);
qemu_put_sbe32s(f, &env->CP0_Wired);
qemu_put_sbe32s(f, &env->CP0_SRSConf0);
qemu_put_sbe32s(f, &env->CP0_SRSConf1);
qemu_put_sbe32s(f, &env->CP0_SRSConf2);
qemu_put_sbe32s(f, &env->CP0_SRSConf3);
qemu_put_sbe32s(f, &env->CP0_SRSConf4);
qemu_put_sbe32s(f, &env->CP0_HWREna);
qemu_put_betls(f, &env->CP0_BadVAddr);
qemu_put_sbe32s(f, &env->CP0_Count);
qemu_put_betls(f, &env->CP0_EntryHi);
qemu_put_sbe32s(f, &env->CP0_Compare);
qemu_put_sbe32s(f, &env->CP0_Status);
qemu_put_sbe32s(f, &env->CP0_IntCtl);
qemu_put_sbe32s(f, &env->CP0_SRSCtl);
qemu_put_sbe32s(f, &env->CP0_SRSMap);
qemu_put_sbe32s(f, &env->CP0_Cause);
qemu_put_betls(f, &env->CP0_EPC);
qemu_put_sbe32s(f, &env->CP0_PRid);
qemu_put_sbe32s(f, &env->CP0_EBase);
qemu_put_sbe32s(f, &env->CP0_Config0);
qemu_put_sbe32s(f, &env->CP0_Config1);
qemu_put_sbe32s(f, &env->CP0_Config2);
qemu_put_sbe32s(f, &env->CP0_Config3);
qemu_put_sbe32s(f, &env->CP0_Config6);
qemu_put_sbe32s(f, &env->CP0_Config7);
qemu_put_betls(f, &env->lladdr);
for(i = 0; i < 8; i++)
qemu_put_betls(f, &env->CP0_WatchLo[i]);
for(i = 0; i < 8; i++)
qemu_put_sbe32s(f, &env->CP0_WatchHi[i]);
qemu_put_betls(f, &env->CP0_XContext);
qemu_put_sbe32s(f, &env->CP0_Framemask);
qemu_put_sbe32s(f, &env->CP0_Debug);
qemu_put_betls(f, &env->CP0_DEPC);
qemu_put_sbe32s(f, &env->CP0_Performance0);
qemu_put_sbe32s(f, &env->CP0_TagLo);
qemu_put_sbe32s(f, &env->CP0_DataLo);
qemu_put_sbe32s(f, &env->CP0_TagHi);
qemu_put_sbe32s(f, &env->CP0_DataHi);
qemu_put_betls(f, &env->CP0_ErrorEPC);
qemu_put_sbe32s(f, &env->CP0_DESAVE);
/* Save inactive TC state */
for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
save_tc(f, &env->tcs[i]);
for (i = 0; i < MIPS_FPU_MAX; i++)
save_fpu(f, &env->fpus[i]);
}
void cpu_save(QEMUFile *f, void *opaque)
{
CPUState *env = opaque;
uint16_t fptag, fpus, fpuc, fpregs_format;
uint32_t hflags;
int32_t a20_mask;
int i;
for(i = 0; i < CPU_NB_REGS; i++)
qemu_put_betls(f, &env->regs[i]);
qemu_put_betls(f, &env->eip);
qemu_put_betls(f, &env->eflags);
hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
qemu_put_be32s(f, &hflags);
/* FPU */
fpuc = env->fpuc;
fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
fptag = 0;
for(i = 0; i < 8; i++) {
fptag |= ((!env->fptags[i]) << i);
}
qemu_put_be16s(f, &fpuc);
qemu_put_be16s(f, &fpus);
qemu_put_be16s(f, &fptag);
#ifdef USE_X86LDOUBLE
fpregs_format = 0;
#else
fpregs_format = 1;
#endif
qemu_put_be16s(f, &fpregs_format);
for(i = 0; i < 8; i++) {
#ifdef USE_X86LDOUBLE
{
uint64_t mant;
uint16_t exp;
/* we save the real CPU data (in case of MMX usage only 'mant'
contains the MMX register */
cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
qemu_put_be64(f, mant);
qemu_put_be16(f, exp);
}
#else
/* if we use doubles for float emulation, we save the doubles to
avoid losing information in case of MMX usage. It can give
problems if the image is restored on a CPU where long
doubles are used instead. */
qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
#endif
}
for(i = 0; i < 6; i++)
cpu_put_seg(f, &env->segs[i]);
cpu_put_seg(f, &env->ldt);
cpu_put_seg(f, &env->tr);
cpu_put_seg(f, &env->gdt);
cpu_put_seg(f, &env->idt);
qemu_put_be32s(f, &env->sysenter_cs);
qemu_put_betls(f, &env->sysenter_esp);
qemu_put_betls(f, &env->sysenter_eip);
qemu_put_betls(f, &env->cr[0]);
qemu_put_betls(f, &env->cr[2]);
qemu_put_betls(f, &env->cr[3]);
qemu_put_betls(f, &env->cr[4]);
for(i = 0; i < 8; i++)
qemu_put_betls(f, &env->dr[i]);
/* MMU */
a20_mask = (int32_t) env->a20_mask;
qemu_put_sbe32s(f, &a20_mask);
/* XMM */
qemu_put_be32s(f, &env->mxcsr);
for(i = 0; i < CPU_NB_REGS; i++) {
qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
}
#ifdef TARGET_X86_64
qemu_put_be64s(f, &env->efer);
qemu_put_be64s(f, &env->star);
qemu_put_be64s(f, &env->lstar);
qemu_put_be64s(f, &env->cstar);
qemu_put_be64s(f, &env->fmask);
qemu_put_be64s(f, &env->kernelgsbase);
#endif
qemu_put_be32s(f, &env->smbase);
qemu_put_be64s(f, &env->pat);
qemu_put_be32s(f, &env->hflags2);
qemu_put_be64s(f, &env->vm_hsave);
qemu_put_be64s(f, &env->vm_vmcb);
qemu_put_be64s(f, &env->tsc_offset);
qemu_put_be64s(f, &env->intercept);
qemu_put_be16s(f, &env->intercept_cr_read);
qemu_put_be16s(f, &env->intercept_cr_write);
qemu_put_be16s(f, &env->intercept_dr_read);
qemu_put_be16s(f, &env->intercept_dr_write);
qemu_put_be32s(f, &env->intercept_exceptions);
qemu_put_8s(f, &env->v_tpr);
/* MTRRs */
for(i = 0; i < 11; i++)
qemu_put_be64s(f, &env->mtrr_fixed[i]);
qemu_put_be64s(f, &env->mtrr_deftype);
for(i = 0; i < 8; i++) {
qemu_put_be64s(f, &env->mtrr_var[i].base);
qemu_put_be64s(f, &env->mtrr_var[i].mask);
}
}
void cpu_save(QEMUFile *f, void *opaque)
{
CPUState *env = opaque;
uint16_t fptag, fpus, fpuc, fpregs_format;
uint32_t hflags;
int32_t a20_mask;
int32_t pending_irq;
int i, bit;
if (kvm_enabled()) {
kvm_save_registers(env);
kvm_arch_save_mpstate(env);
}
for(i = 0; i < CPU_NB_REGS; i++)
qemu_put_betls(f, &env->regs[i]);
qemu_put_betls(f, &env->eip);
qemu_put_betls(f, &env->eflags);
hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
qemu_put_be32s(f, &hflags);
/* FPU */
fpuc = env->fpuc;
fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
fptag = 0;
for(i = 0; i < 8; i++) {
fptag |= ((!env->fptags[i]) << i);
}
qemu_put_be16s(f, &fpuc);
qemu_put_be16s(f, &fpus);
qemu_put_be16s(f, &fptag);
#ifdef USE_X86LDOUBLE
fpregs_format = 0;
#else
fpregs_format = 1;
#endif
qemu_put_be16s(f, &fpregs_format);
for(i = 0; i < 8; i++) {
#ifdef USE_X86LDOUBLE
{
uint64_t mant;
uint16_t exp;
/* we save the real CPU data (in case of MMX usage only 'mant'
contains the MMX register */
cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
qemu_put_be64(f, mant);
qemu_put_be16(f, exp);
}
#else
/* if we use doubles for float emulation, we save the doubles to
avoid losing information in case of MMX usage. It can give
problems if the image is restored on a CPU where long
doubles are used instead. */
qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
#endif
}
for(i = 0; i < 6; i++)
cpu_put_seg(f, &env->segs[i]);
cpu_put_seg(f, &env->ldt);
cpu_put_seg(f, &env->tr);
cpu_put_seg(f, &env->gdt);
cpu_put_seg(f, &env->idt);
qemu_put_be32s(f, &env->sysenter_cs);
qemu_put_betls(f, &env->sysenter_esp);
qemu_put_betls(f, &env->sysenter_eip);
qemu_put_betls(f, &env->cr[0]);
qemu_put_betls(f, &env->cr[2]);
qemu_put_betls(f, &env->cr[3]);
qemu_put_betls(f, &env->cr[4]);
for(i = 0; i < 8; i++)
qemu_put_betls(f, &env->dr[i]);
/* MMU */
a20_mask = (int32_t) env->a20_mask;
qemu_put_sbe32s(f, &a20_mask);
/* XMM */
qemu_put_be32s(f, &env->mxcsr);
for(i = 0; i < CPU_NB_REGS; i++) {
qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
}
#ifdef TARGET_X86_64
qemu_put_be64s(f, &env->efer);
qemu_put_be64s(f, &env->star);
qemu_put_be64s(f, &env->lstar);
qemu_put_be64s(f, &env->cstar);
qemu_put_be64s(f, &env->fmask);
qemu_put_be64s(f, &env->kernelgsbase);
#endif
qemu_put_be32s(f, &env->smbase);
qemu_put_be64s(f, &env->pat);
qemu_put_be32s(f, &env->hflags2);
qemu_put_be64s(f, &env->vm_hsave);
qemu_put_be64s(f, &env->vm_vmcb);
qemu_put_be64s(f, &env->tsc_offset);
qemu_put_be64s(f, &env->intercept);
qemu_put_be16s(f, &env->intercept_cr_read);
qemu_put_be16s(f, &env->intercept_cr_write);
qemu_put_be16s(f, &env->intercept_dr_read);
qemu_put_be16s(f, &env->intercept_dr_write);
qemu_put_be32s(f, &env->intercept_exceptions);
qemu_put_8s(f, &env->v_tpr);
/* MTRRs */
for(i = 0; i < 11; i++)
qemu_put_be64s(f, &env->mtrr_fixed[i]);
qemu_put_be64s(f, &env->mtrr_deftype);
for(i = 0; i < 8; i++) {
qemu_put_be64s(f, &env->mtrr_var[i].base);
qemu_put_be64s(f, &env->mtrr_var[i].mask);
}
/* KVM-related states */
/* There can only be one pending IRQ set in the bitmap at a time, so try
to find it and save its number instead (-1 for none). */
pending_irq = -1;
for (i = 0; i < ARRAY_SIZE(env->interrupt_bitmap); i++) {
if (env->interrupt_bitmap[i]) {
bit = ctz64(env->interrupt_bitmap[i]);
pending_irq = i * 64 + bit;
break;
}
}
qemu_put_sbe32s(f, &pending_irq);
qemu_put_be32s(f, &env->mp_state);
qemu_put_be64s(f, &env->tsc);
/* MCE */
qemu_put_be64s(f, &env->mcg_cap);
if (env->mcg_cap && !kvm_enabled()) {
qemu_put_be64s(f, &env->mcg_status);
qemu_put_be64s(f, &env->mcg_ctl);
for (i = 0; i < (env->mcg_cap & 0xff); i++) {
qemu_put_be64s(f, &env->mce_banks[4*i]);
qemu_put_be64s(f, &env->mce_banks[4*i + 1]);
qemu_put_be64s(f, &env->mce_banks[4*i + 2]);
qemu_put_be64s(f, &env->mce_banks[4*i + 3]);
}
}
}
void cpu_save(QEMUFile *f, void *opaque)
{
CPUPPCState *env = (CPUPPCState *)opaque;
unsigned int i, j;
uint32_t fpscr;
for (i = 0; i < 32; i++)
qemu_put_betls(f, &env->gpr[i]);
#if !defined(TARGET_PPC64)
for (i = 0; i < 32; i++)
qemu_put_betls(f, &env->gprh[i]);
#endif
qemu_put_betls(f, &env->lr);
qemu_put_betls(f, &env->ctr);
for (i = 0; i < 8; i++)
qemu_put_be32s(f, &env->crf[i]);
qemu_put_betls(f, &env->xer);
qemu_put_betls(f, &env->reserve_addr);
qemu_put_betls(f, &env->msr);
for (i = 0; i < 4; i++)
qemu_put_betls(f, &env->tgpr[i]);
for (i = 0; i < 32; i++) {
union {
float64 d;
uint64_t l;
} u;
u.d = env->fpr[i];
qemu_put_be64(f, u.l);
}
fpscr = env->fpscr;
qemu_put_be32s(f, &fpscr);
qemu_put_sbe32s(f, &env->access_type);
#if defined(TARGET_PPC64)
qemu_put_betls(f, &env->asr);
qemu_put_sbe32s(f, &env->slb_nr);
#endif
qemu_put_betls(f, &env->spr[SPR_SDR1]);
for (i = 0; i < 32; i++)
qemu_put_betls(f, &env->sr[i]);
for (i = 0; i < 2; i++)
for (j = 0; j < 8; j++)
qemu_put_betls(f, &env->DBAT[i][j]);
for (i = 0; i < 2; i++)
for (j = 0; j < 8; j++)
qemu_put_betls(f, &env->IBAT[i][j]);
qemu_put_sbe32s(f, &env->nb_tlb);
qemu_put_sbe32s(f, &env->tlb_per_way);
qemu_put_sbe32s(f, &env->nb_ways);
qemu_put_sbe32s(f, &env->last_way);
qemu_put_sbe32s(f, &env->id_tlbs);
qemu_put_sbe32s(f, &env->nb_pids);
if (env->tlb.tlb6) {
// XXX assumes 6xx
for (i = 0; i < env->nb_tlb; i++) {
qemu_put_betls(f, &env->tlb.tlb6[i].pte0);
qemu_put_betls(f, &env->tlb.tlb6[i].pte1);
qemu_put_betls(f, &env->tlb.tlb6[i].EPN);
}
}
for (i = 0; i < 4; i++)
qemu_put_betls(f, &env->pb[i]);
for (i = 0; i < 1024; i++)
qemu_put_betls(f, &env->spr[i]);
qemu_put_be32s(f, &env->vscr);
qemu_put_be64s(f, &env->spe_acc);
qemu_put_be32s(f, &env->spe_fscr);
qemu_put_betls(f, &env->msr_mask);
qemu_put_be32s(f, &env->flags);
qemu_put_sbe32s(f, &env->error_code);
qemu_put_be32s(f, &env->pending_interrupts);
qemu_put_be32s(f, &env->irq_input_state);
for (i = 0; i < POWERPC_EXCP_NB; i++)
qemu_put_betls(f, &env->excp_vectors[i]);
qemu_put_betls(f, &env->excp_prefix);
qemu_put_betls(f, &env->hreset_excp_prefix);
qemu_put_betls(f, &env->ivor_mask);
qemu_put_betls(f, &env->ivpr_mask);
qemu_put_betls(f, &env->hreset_vector);
qemu_put_betls(f, &env->nip);
qemu_put_betls(f, &env->hflags);
qemu_put_betls(f, &env->hflags_nmsr);
qemu_put_sbe32s(f, &env->mmu_idx);
qemu_put_sbe32(f, 0);
}
void cpu_save(QEMUFile *f, void *opaque)
{
CPUSPARCState *env = opaque;
int i;
uint32_t tmp;
// if env->cwp == env->nwindows - 1, this will set the ins of the last
// window as the outs of the first window
cpu_set_cwp(env, env->cwp);
for(i = 0; i < 8; i++)
qemu_put_betls(f, &env->gregs[i]);
qemu_put_be32s(f, &env->nwindows);
for(i = 0; i < env->nwindows * 16; i++)
qemu_put_betls(f, &env->regbase[i]);
/* FPU */
for (i = 0; i < TARGET_DPREGS; i++) {
qemu_put_be32(f, env->fpr[i].l.upper);
qemu_put_be32(f, env->fpr[i].l.lower);
}
qemu_put_betls(f, &env->pc);
qemu_put_betls(f, &env->npc);
qemu_put_betls(f, &env->y);
tmp = cpu_get_psr(env);
qemu_put_be32(f, tmp);
qemu_put_betls(f, &env->fsr);
qemu_put_betls(f, &env->tbr);
tmp = env->interrupt_index;
qemu_put_be32(f, tmp);
qemu_put_be32s(f, &env->pil_in);
#ifndef TARGET_SPARC64
qemu_put_be32s(f, &env->wim);
/* MMU */
for (i = 0; i < 32; i++)
qemu_put_be32s(f, &env->mmuregs[i]);
for (i = 0; i < 4; i++) {
qemu_put_be64s(f, &env->mxccdata[i]);
}
for (i = 0; i < 8; i++) {
qemu_put_be64s(f, &env->mxccregs[i]);
}
qemu_put_be32s(f, &env->mmubpctrv);
qemu_put_be32s(f, &env->mmubpctrc);
qemu_put_be32s(f, &env->mmubpctrs);
qemu_put_be64s(f, &env->mmubpaction);
for (i = 0; i < 4; i++) {
qemu_put_be64s(f, &env->mmubpregs[i]);
}
#else
qemu_put_be64s(f, &env->lsu);
for (i = 0; i < 16; i++) {
qemu_put_be64s(f, &env->immuregs[i]);
qemu_put_be64s(f, &env->dmmuregs[i]);
}
for (i = 0; i < 64; i++) {
qemu_put_be64s(f, &env->itlb[i].tag);
qemu_put_be64s(f, &env->itlb[i].tte);
qemu_put_be64s(f, &env->dtlb[i].tag);
qemu_put_be64s(f, &env->dtlb[i].tte);
}
qemu_put_be32s(f, &env->mmu_version);
for (i = 0; i < MAXTL_MAX; i++) {
qemu_put_be64s(f, &env->ts[i].tpc);
qemu_put_be64s(f, &env->ts[i].tnpc);
qemu_put_be64s(f, &env->ts[i].tstate);
qemu_put_be32s(f, &env->ts[i].tt);
}
qemu_put_be32s(f, &env->xcc);
qemu_put_be32s(f, &env->asi);
qemu_put_be32s(f, &env->pstate);
qemu_put_be32s(f, &env->tl);
qemu_put_be32s(f, &env->cansave);
qemu_put_be32s(f, &env->canrestore);
qemu_put_be32s(f, &env->otherwin);
qemu_put_be32s(f, &env->wstate);
qemu_put_be32s(f, &env->cleanwin);
for (i = 0; i < 8; i++)
qemu_put_be64s(f, &env->agregs[i]);
for (i = 0; i < 8; i++)
qemu_put_be64s(f, &env->bgregs[i]);
for (i = 0; i < 8; i++)
qemu_put_be64s(f, &env->igregs[i]);
for (i = 0; i < 8; i++)
qemu_put_be64s(f, &env->mgregs[i]);
qemu_put_be64s(f, &env->fprs);
qemu_put_be64s(f, &env->tick_cmpr);
qemu_put_be64s(f, &env->stick_cmpr);
cpu_put_timer(f, env->tick);
cpu_put_timer(f, env->stick);
qemu_put_be64s(f, &env->gsr);
qemu_put_be32s(f, &env->gl);
qemu_put_be64s(f, &env->hpstate);
for (i = 0; i < MAXTL_MAX; i++)
qemu_put_be64s(f, &env->htstate[i]);
qemu_put_be64s(f, &env->hintp);
qemu_put_be64s(f, &env->htba);
qemu_put_be64s(f, &env->hver);
qemu_put_be64s(f, &env->hstick_cmpr);
qemu_put_be64s(f, &env->ssr);
cpu_put_timer(f, env->hstick);
#endif
}
void cpu_save(QEMUFile *f, void *opaque)
{
CPUState *env = opaque;
uint16_t fptag, fpus, fpuc, fpregs_format;
uint32_t hflags;
int32_t a20_mask;
int i;
cpu_synchronize_state(env, 0);
for(i = 0; i < CPU_NB_REGS; i++)
qemu_put_betls(f, &env->regs[i]);
qemu_put_betls(f, &env->eip);
qemu_put_betls(f, &env->eflags);
hflags = env->hflags;
qemu_put_be32s(f, &hflags);
fpuc = env->fpuc;
fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
fptag = 0;
for(i = 0; i < 8; i++) {
fptag |= ((!env->fptags[i]) << i);
}
qemu_put_be16s(f, &fpuc);
qemu_put_be16s(f, &fpus);
qemu_put_be16s(f, &fptag);
#ifdef USE_X86LDOUBLE
fpregs_format = 0;
#else
fpregs_format = 1;
#endif
qemu_put_be16s(f, &fpregs_format);
for(i = 0; i < 8; i++) {
#ifdef USE_X86LDOUBLE
{
uint64_t mant;
uint16_t exp;
cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
qemu_put_be64(f, mant);
qemu_put_be16(f, exp);
}
#else
qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
#endif
}
for(i = 0; i < 6; i++)
cpu_put_seg(f, &env->segs[i]);
cpu_put_seg(f, &env->ldt);
cpu_put_seg(f, &env->tr);
cpu_put_seg(f, &env->gdt);
cpu_put_seg(f, &env->idt);
qemu_put_be32s(f, &env->sysenter_cs);
qemu_put_betls(f, &env->sysenter_esp);
qemu_put_betls(f, &env->sysenter_eip);
qemu_put_betls(f, &env->cr[0]);
qemu_put_betls(f, &env->cr[2]);
qemu_put_betls(f, &env->cr[3]);
qemu_put_betls(f, &env->cr[4]);
for(i = 0; i < 8; i++)
qemu_put_betls(f, &env->dr[i]);
a20_mask = (int32_t) env->a20_mask;
qemu_put_sbe32s(f, &a20_mask);
qemu_put_be32s(f, &env->mxcsr);
for(i = 0; i < CPU_NB_REGS; i++) {
qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
}
#ifdef TARGET_X86_64
qemu_put_be64s(f, &env->efer);
qemu_put_be64s(f, &env->star);
qemu_put_be64s(f, &env->lstar);
qemu_put_be64s(f, &env->cstar);
qemu_put_be64s(f, &env->fmask);
qemu_put_be64s(f, &env->kernelgsbase);
#endif
qemu_put_be32s(f, &env->smbase);
qemu_put_be64s(f, &env->pat);
qemu_put_be32s(f, &env->hflags2);
qemu_put_be64s(f, &env->vm_hsave);
qemu_put_be64s(f, &env->vm_vmcb);
qemu_put_be64s(f, &env->tsc_offset);
qemu_put_be64s(f, &env->intercept);
qemu_put_be16s(f, &env->intercept_cr_read);
qemu_put_be16s(f, &env->intercept_cr_write);
qemu_put_be16s(f, &env->intercept_dr_read);
qemu_put_be16s(f, &env->intercept_dr_write);
qemu_put_be32s(f, &env->intercept_exceptions);
qemu_put_8s(f, &env->v_tpr);
for(i = 0; i < 11; i++)
qemu_put_be64s(f, &env->mtrr_fixed[i]);
qemu_put_be64s(f, &env->mtrr_deftype);
for(i = 0; i < 8; i++) {
qemu_put_be64s(f, &env->mtrr_var[i].base);
qemu_put_be64s(f, &env->mtrr_var[i].mask);
}
for (i = 0; i < sizeof(env->interrupt_bitmap)/8; i++) {
qemu_put_be64s(f, &env->interrupt_bitmap[i]);
}
qemu_put_be64s(f, &env->tsc);
qemu_put_be32s(f, &env->mp_state);
qemu_put_be64s(f, &env->mcg_cap);
if (env->mcg_cap) {
qemu_put_be64s(f, &env->mcg_status);
qemu_put_be64s(f, &env->mcg_ctl);
for (i = 0; i < (env->mcg_cap & 0xff); i++) {
qemu_put_be64s(f, &env->mce_banks[4*i]);
qemu_put_be64s(f, &env->mce_banks[4*i + 1]);
qemu_put_be64s(f, &env->mce_banks[4*i + 2]);
qemu_put_be64s(f, &env->mce_banks[4*i + 3]);
}
}
}