static int macronix_quad_enable(qspi_flash_t *flash)
{
int ret, val;
val = qspi_flash_read_status_reg(flash);
if (val < 0)
return val;
if (val & SR_QUAD_EN_MX)
return 0;
dbg_info("QSPI Flash: Macronix Quad mode disabled, enable it\n");
ret = qspi_flash_write_enable(flash);
if (ret)
return ret;
ret = qspi_flash_write_status_reg(flash, val | SR_QUAD_EN_MX);
if (ret)
return ret;
ret = qspi_flash_wait_ready(flash);
if (ret)
return ret;
ret = qspi_flash_read_status_reg(flash);
if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
dbg_info("QSPI Flash: Macronix Quad bit not set\n");
return -1;
}
return 0;
}
static inline int qspi_flash_ready(qspi_flash_t *flash)
{
int sr = qspi_flash_read_status_reg(flash);
if (sr < 0)
return sr;
else
return !(sr & STATUS_WRITE_BUSY);
}
static int qspi_flash_enable_write(void)
{
qspi_frame_t *frame = &qspi_frame;
unsigned char status;
qspi_init_frame(frame);
frame->instruction = CMD_WRITE_ENABLE;
frame->tansfer_type = read;
frame->protocol = spi_mode;
qspi_send_command(frame, 0);
status = qspi_flash_read_status_reg();
if (status & STATUS_WRITE_ENABLE_SET)
return 0;
else
return -1;
}
static int macronix_set_dummy_cycles(qspi_flash_t *flash,
unsigned char num_dummy_cycles)
{
int ret, sr, cr, mask, val;
unsigned char dc, sr_cr[2];
/* Convert the numver of dummy cycles into Macronix DC volatile bits. */
ret = macronix_dummy2code(flash->read_opcode, num_dummy_cycles, &dc);
if (ret)
return ret;
mask = 0xc0;
val = (dc << 6) & mask;
cr = qspi_flash_read_macronix_config_reg(flash);
if (cr < 0) {
dbg_info("QSPI Flash: error while reading CR register\n");
return cr;
}
if ((cr & mask) == val)
goto updated;
sr = qspi_flash_read_status_reg(flash);
if (sr < 0) {
dbg_info("QSPI Flash: error while reading SR register\n");
return sr;
}
ret = qspi_flash_write_enable(flash);
if (ret)
return ret;
cr = (cr & ~mask) | val;
sr_cr[0] = sr & 0xff;
sr_cr[1] = cr & 0xff;
ret = qspi_flash_write_status_and_config_regs(flash, sr_cr);
if (ret) {
dbg_info("QSPI Flash: error while writing SR and CR registers\n");
return ret;
}
ret = qspi_flash_wait_ready(flash);
if (ret)
return ret;
cr = qspi_flash_read_macronix_config_reg(flash);
if (cr < 0 || (cr & mask) != val) {
dbg_info("QSPI Flash: Macronix Dummy Cycle bits not updated\n");
return -1;
}
updated:
if (num_dummy_cycles) {
flash->num_mode_cycles = 2;
flash->num_dummy_cycles = num_dummy_cycles - 2;
} else {
flash->num_mode_cycles = 0;
flash->num_dummy_cycles = 0;
}
/* mode cycles: bit[0:3] = ~bit[4:7]: continuous read, normal read otherwise */
flash->normal_mode = 0x00;
flash->continuous_read_mode = 0xf0;
return 0;
}
