static void pwm_timer_init(unsigned timer) { /* enable the timer clock before we try to talk to it */ modifyreg32(pwm_timers[timer].clock_register, 0, pwm_timers[timer].clock_bit); /* disable and configure the timer */ rCR1(timer) = 0; rCR2(timer) = 0; rSMCR(timer) = 0; rDIER(timer) = 0; rCCER(timer) = 0; rCCMR1(timer) = 0; rCCMR2(timer) = 0; rCCER(timer) = 0; rDCR(timer) = 0; /* configure the timer to free-run at 1MHz */ rPSC(timer) = (pwm_timers[timer].clock_freq / 1000000) - 1; /* default to updating at 50Hz */ pwm_timer_set_rate(timer, 50); /* note that the timer is left disabled - arming is performed separately */ }
static void pwm_channel_init(unsigned channel) { unsigned timer = cfg->channels[channel].timer_index; /* configure the GPIO first */ stm32_configgpio(cfg->channels[channel].gpio); /* configure the channel */ switch (cfg->channels[channel].timer_channel) { case 1: rCCMR1(timer) |= (6 << 4); rCCR1(timer) = cfg->channels[channel].default_value; rCCER(timer) |= (1 << 0); break; case 2: rCCMR1(timer) |= (6 << 12); rCCR2(timer) = cfg->channels[channel].default_value; rCCER(timer) |= (1 << 4); break; case 3: rCCMR2(timer) |= (6 << 4); rCCR3(timer) = cfg->channels[channel].default_value; rCCER(timer) |= (1 << 8); break; case 4: rCCMR2(timer) |= (6 << 12); rCCR4(timer) = cfg->channels[channel].default_value; rCCER(timer) |= (1 << 12); break; } }
static void pwm_channel_init(unsigned channel) { unsigned timer = pwm_channels[channel].timer_index; /* configure the GPIO first */ stm32_configgpio(pwm_channels[channel].gpio); /* configure the channel */ switch (pwm_channels[channel].timer_channel) { case 1: rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) | GTIM_CCMR1_OC1PE; rCCR1(timer) = pwm_channels[channel].default_value; rCCER(timer) |= GTIM_CCER_CC1E; break; case 2: rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC2M_SHIFT) | GTIM_CCMR1_OC2PE; rCCR2(timer) = pwm_channels[channel].default_value; rCCER(timer) |= GTIM_CCER_CC2E; break; case 3: rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC3M_SHIFT) | GTIM_CCMR2_OC3PE; rCCR3(timer) = pwm_channels[channel].default_value; rCCER(timer) |= GTIM_CCER_CC3E; break; case 4: rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC4M_SHIFT) | GTIM_CCMR2_OC4PE; rCCR4(timer) = pwm_channels[channel].default_value; rCCER(timer) |= GTIM_CCER_CC4E; break; } }
static void pwm_input_timer_init(unsigned timer) { /* enable the timer clock before we try to talk to it */ modifyreg32(pwm_input_timers[timer].clock_register, 0, pwm_input_timers[timer].clock_bit); /* disable and configure the timer */ rCR1(timer) |= 0; rCR2(timer) |= 0; rSMCR(timer) |= 0; rDIER(timer) |= 0; rCCER(timer) |= 0; rCCMR1(timer) |= 0; rCCMR2(timer) |= 0; rCCER(timer) |= 0; rDCR(timer) |= 0; // if ((pwm_input_timers[timer].base == STM32_TIM1_BASE) || (pwm_input_timers[timer].base == STM32_TIM8_BASE)) { // /* master output enable = on */ // rBDTR(timer) = ATIM_BDTR_MOE; // } /* configure the timer to free-run at 1MHz */ rPSC(timer) |= (pwm_input_timers[timer].clock_freq / 1000000) - 1; /* run the full span of the counter */ rARR(timer) |= 0xffff; /* generate an update event; reloads the counter, all registers */ rEGR(timer) |= GTIM_EGR_UG ; /* enable the timer */ rCR1(timer) |= GTIM_CR1_CEN; }
static void pwm_timer_init(unsigned timer) { /* enable the timer clock before we try to talk to it */ modifyreg32(cfg->timers[timer].clock_register, 0, cfg->timers[timer].clock_bit); /* disable and configure the timer */ rCR1(timer) = 0; rCR2(timer) = 0; rSMCR(timer) = 0; rDIER(timer) = 0; rCCER(timer) = 0; rCCMR1(timer) = 0; rCCMR2(timer) = 0; rCCER(timer) = 0; rDCR(timer) = 0; /* configure the timer to free-run at 1MHz */ rPSC(timer) = cfg->timers[timer].clock_freq / 1000000; /* and update at the desired rate */ rARR(timer) = 1000000 / cfg->update_rate; /* generate an update event; reloads the counter and all registers */ rEGR(timer) = GTIM_EGR_UG; /* note that the timer is left disabled - arming is performed separately */ }
static void input_pwm_timer_init(unsigned timer) { /* enable the timer clock before we try to talk to it */ modifyreg32(input_pwm_timers[timer].clock_register, 0, input_pwm_timers[timer].clock_bit); /* disable and configure the timer */ rCR1(timer) = 0; rCR2(timer) = 0; rSMCR(timer) = 0; rDIER(timer) = 0; rCCER(timer) = 0; rCCMR1(timer) = 0; rCCMR2(timer) = 0; rCCER(timer) = 0; rDCR(timer) = 0; /* configure the timer to free-run at 1MHz */ rPSC(timer) = (input_pwm_timers[timer].clock_freq / 1000000) - 1; /* run the full span of the counter */ rARR(timer) = 0xffff; /* generate an update event; reloads the counter, all registers */ rEGR(timer) = GTIM_EGR_UG; /* enable the timer and disable the update flag event */ rCR1(timer) = GTIM_CR1_UDIS | GTIM_CR1_CEN; }
static void led_pwm_channel_init(unsigned channel) { unsigned timer = led_pwm_channels[channel].timer_index; /* configure the GPIO first */ px4_arch_configgpio(led_pwm_channels[channel].gpio_out); /* configure the channel */ switch (led_pwm_channels[channel].timer_channel) { case 1: rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) | GTIM_CCMR1_OC1PE; rCCER(timer) |= GTIM_CCER_CC1E; break; case 2: rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC2M_SHIFT) | GTIM_CCMR1_OC2PE; rCCER(timer) |= GTIM_CCER_CC2E; break; case 3: rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC3M_SHIFT) | GTIM_CCMR2_OC3PE; rCCER(timer) |= GTIM_CCER_CC3E; break; case 4: rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC4M_SHIFT) | GTIM_CCMR2_OC4PE; rCCER(timer) |= GTIM_CCER_CC4E; break; } }
static void led_pwm_timer_init_timer(unsigned timer) { irqstate_t flags = px4_enter_critical_section(); /* enable the timer clock before we try to talk to it */ modifyreg32(led_pwm_timers[timer].clock_register, 0, led_pwm_timers[timer].clock_bit); /* disable and configure the timer */ rCR1(timer) = 0; rCR2(timer) = 0; rSMCR(timer) = 0; rDIER(timer) = 0; rCCER(timer) = 0; rCCMR1(timer) = 0; rCCMR2(timer) = 0; rCCR1(timer) = 0; rCCR2(timer) = 0; rCCR3(timer) = 0; rCCR4(timer) = 0; rCCER(timer) = 0; rDCR(timer) = 0; if ((led_pwm_timers[timer].base == STM32_TIM1_BASE) || (led_pwm_timers[timer].base == STM32_TIM8_BASE)) { /* master output enable = on */ rBDTR(timer) = ATIM_BDTR_MOE; } /* If the timer clock source provided as clock_freq is the STM32_APBx_TIMx_CLKIN * then configure the timer to free-run at 1MHz. * Otherwise, other frequencies are attainable by adjusting .clock_freq accordingly. */ rPSC(timer) = (led_pwm_timers[timer].clock_freq / 1000000) - 1; /* configure the timer to update at the desired rate */ rARR(timer) = (1000000 / LED_PWM_RATE) - 1; /* generate an update event; reloads the counter and all registers */ rEGR(timer) = GTIM_EGR_UG; px4_leave_critical_section(flags); }
static void led_pwm_channel_init(unsigned channel) { /* Only initialize used channels */ if (led_pwm_channels[channel].timer_channel) { unsigned timer = led_pwm_channels[channel].timer_index; printf("init led pwm timer #%d, channel #%d\n", timer, channel); /* configure the GPIO first */ px4_arch_configgpio(led_pwm_channels[channel].gpio_out); uint16_t polarity = 0; //led_pwm_channels[channel].masks; printf("polarity for channel #%d: %d\n", channel, polarity); /* configure the channel */ switch (led_pwm_channels[channel].timer_channel) { case 1: rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) | GTIM_CCMR1_OC1PE; rCCER(timer) |= polarity | GTIM_CCER_CC1E; break; case 2: rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC2M_SHIFT) | GTIM_CCMR1_OC2PE; rCCER(timer) |= polarity | GTIM_CCER_CC2E; break; case 3: rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC3M_SHIFT) | GTIM_CCMR2_OC3PE; rCCER(timer) |= polarity | GTIM_CCER_CC3E; break; case 4: rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC4M_SHIFT) | GTIM_CCMR2_OC4PE; rCCER(timer) |= polarity | GTIM_CCER_CC4E; break; } } }
static void pwm_input_channel_init(unsigned channel) { unsigned timer = pwm_input_channels[channel].timer_index; /* configure the GPIO first */ stm32_configgpio(pwm_input_channels[channel].gpio); /* configure the channel */ switch (pwm_input_channels[channel].timer_channel) { case 1: rCCMR1(timer) |= (GTIM_CCMR_CCS_CCIN1<<GTIM_CCMR1_CC1S_SHIFT)|(GTIM_CCMR_ICF_FCKINT8<<GTIM_CCMR1_IC1F_SHIFT); rCCER(timer) |= GTIM_CCER_CC1E|GTIM_CCER_CC1P|GTIM_CCER_CC1NP; rDIER(timer) |= GTIM_DIER_CC1IE; break; case 2: rCCMR1(timer) |= (GTIM_CCMR_CCS_CCIN1<<GTIM_CCMR1_CC2S_SHIFT)|(GTIM_CCMR_ICF_FCKINT8<<GTIM_CCMR1_IC2F_SHIFT); rCCER(timer) |= GTIM_CCER_CC2E|GTIM_CCER_CC2P|GTIM_CCER_CC2NP; rDIER(timer) |= GTIM_DIER_CC2IE; break; case 3: rCCMR2(timer) |= (GTIM_CCMR_CCS_CCIN1<<GTIM_CCMR2_CC3S_SHIFT)|(GTIM_CCMR_ICF_FCKINT8<<GTIM_CCMR2_IC3F_SHIFT); rCCER(timer) |= GTIM_CCER_CC3E|GTIM_CCER_CC3P|GTIM_CCER_CC3NP; rDIER(timer) |= GTIM_DIER_CC3IE; break; case 4: rCCMR2(timer) |= (GTIM_CCMR_CCS_CCIN1<<GTIM_CCMR2_CC4S_SHIFT)|(GTIM_CCMR_ICF_FCKINT8<<GTIM_CCMR2_IC4F_SHIFT); rCCER(timer) |= GTIM_CCER_CC4E|GTIM_CCER_CC4P|GTIM_CCER_CC4NP; rDIER(timer) |= GTIM_DIER_CC4IE; break; } }
static void input_pwm_channel_init(unsigned channel) { unsigned timer = input_pwm_channels[channel].timer_index; /* configure the GPIO first */ stm32_configgpio(input_pwm_channels[channel].gpio); /* configure the channel */ switch (input_pwm_channels[channel].timer_channel) { case 1: rDIER(timer) |= GTIM_DIER_CC1IE; rCCMR1(timer) |= (GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT); rCCR1(timer) = 1000; rCCER(timer) |= GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP; break; case 2: rDIER(timer) |= GTIM_DIER_CC2IE; rCCMR1(timer) |= (GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT); rCCR2(timer) = 1000; rCCER(timer) |= GTIM_CCER_CC2E | GTIM_CCER_CC2P | GTIM_CCER_CC2NP; break; case 3: rDIER(timer) |= GTIM_DIER_CC3IE; rCCMR2(timer) |= (GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR2_CC3S_SHIFT); rCCR3(timer) = 1000; rCCER(timer) |= GTIM_CCER_CC3E | GTIM_CCER_CC3P | GTIM_CCER_CC3NP; break; case 4: rDIER(timer) |= GTIM_DIER_CC4IE; rCCMR2(timer) |= (GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR2_CC4S_SHIFT); rCCR4(timer) = 1000; rCCER(timer) |= GTIM_CCER_CC4E | GTIM_CCER_CC4P | GTIM_CCER_CC4NP; break; } }
static void pwm_channel_init(unsigned channel) { unsigned timer = pwm_channels[channel].timer_index; /* configure the GPIO first */ stm32_configgpio(pwm_channels[channel].gpio); /* configure the channel */ switch (pwm_channels[channel].timer_channel) { case 1: rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) | GTIM_CCMR1_OC1PE; rCCR1(timer) = pwm_channels[channel].default_value; #if defined(CONFIG_ARCH_BOARD_TMRFC_V1) if(channel == 12) rCCER(timer) |= GTIM_CCER_CC1NE; /* complementary output enable */ else #endif rCCER(timer) |= GTIM_CCER_CC1E; break; case 2: rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC2M_SHIFT) | GTIM_CCMR1_OC2PE; rCCR2(timer) = pwm_channels[channel].default_value; #if defined(CONFIG_ARCH_BOARD_TMRFC_V1) if(channel == 6) rCCER(timer) |= GTIM_CCER_CC2NE; /* complementary output enable */ else #endif rCCER(timer) |= GTIM_CCER_CC2E; break; case 3: rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC3M_SHIFT) | GTIM_CCMR2_OC3PE; rCCR3(timer) = pwm_channels[channel].default_value; #if defined(CONFIG_ARCH_BOARD_TMRFC_V1) if(channel == 7) rCCER(timer) |= GTIM_CCER_CC3NE; /* complementary output enable */ else #endif rCCER(timer) |= GTIM_CCER_CC3E; break; case 4: rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC4M_SHIFT) | GTIM_CCMR2_OC4PE; rCCR4(timer) = pwm_channels[channel].default_value; rCCER(timer) |= GTIM_CCER_CC4E; break; } }
static int set_timer(unsigned timer) { /* enable the timer clock before we try to talk to it */ modifyreg32(input_timers[timer].clock_register, 0, input_timers[timer].clock_bit); if(timer == 3) //timer 8 { ArCR1(timer) |= 0; ArCR2(timer) |= 0; ArSMCR(timer) |= 0; ArDIER(timer) |= 0; ArCCER(timer) |= 0; ArCCMR1(timer) |= 0; ArCCMR2(timer) |= 0; ArCCER(timer) |= 0; ArDCR(timer) |= 0; /* configure the timer to free-run at 1MHz */ ArPSC(timer) = (input_timers[timer].clock_freq / 1000000) - 1; if (timer == 2) ArBDTR(timer) |= 0; /* run the full span of the counter */ ArARR(timer) |= 0xffff; } else { /* disable and configure the timer */ rCR1(timer) |= 0; rCR2(timer) |= 0; rSMCR(timer) |= 0; rDIER(timer) |= 0; rCCER(timer) |= 0; rCCMR1(timer) |= 0; rCCMR2(timer) |= 0; rCCER(timer) |= 0; rDCR(timer) |= 0; /* configure the timer to free-run at 1MHz */ rPSC(timer) |= (input_timers[timer].clock_freq / 1000000) - 1; rARR(timer) |= 0xffff; } switch (timer) { case 0: //timer 14 - channel 1 rCCMR1(timer) |= ((GTIM_CCMR_CCS_CCIN1<<GTIM_CCMR1_CC1S_SHIFT)|(GTIM_CCMR_ICF_FCKINT8<<GTIM_CCMR1_IC1F_SHIFT)); rCCMR2(timer) |= 0; rCCER(timer) |= (GTIM_CCER_CC1E|GTIM_CCER_CC1P|GTIM_CCER_CC1NP); rDIER(timer) |= GTIM_DIER_CC1IE; break; case 1: //timer 12 -channel -1 &2 rCCMR1(timer) |= ((GTIM_CCMR_CCS_CCIN1<<GTIM_CCMR1_CC1S_SHIFT)|(GTIM_CCMR_ICF_FCKINT8<<GTIM_CCMR1_IC1F_SHIFT)|(GTIM_CCMR_CCS_CCIN1<<GTIM_CCMR1_CC2S_SHIFT)|(GTIM_CCMR_ICF_FCKINT8<<GTIM_CCMR1_IC1F_SHIFT)); rCCMR2(timer) |= 0; rCCER(timer) |= (GTIM_CCER_CC1E|GTIM_CCER_CC2E|GTIM_CCER_CC1P|GTIM_CCER_CC1NP|GTIM_CCER_CC2P|GTIM_CCER_CC2NP); rDIER(timer) |= (GTIM_DIER_CC1IE|GTIM_DIER_CC2IE); break; case 2://timer 13 - channel 1 rCCMR1(timer) |= ((GTIM_CCMR_CCS_CCIN1<<GTIM_CCMR1_CC1S_SHIFT)|(GTIM_CCMR_ICF_FCKINT8<<GTIM_CCMR1_IC1F_SHIFT)); rCCMR2(timer) |= 0; rCCER(timer) |= (GTIM_CCER_CC1E|GTIM_CCER_CC1P|GTIM_CCER_CC1NP); rDIER(timer) |= GTIM_DIER_CC1IE; break; case 3://timer 8 - channel 1&2 ArCCMR1(timer) |= ((ATIM_CCMR_CCS_CCIN1<<ATIM_CCMR1_CC1S_SHIFT)|(ATIM_CCMR_ICF_FCKINT8<<ATIM_CCMR1_IC1F_SHIFT)|(ATIM_CCMR_CCS_CCIN1<<ATIM_CCMR1_CC2S_SHIFT)|(ATIM_CCMR_ICF_FCKINT8<<ATIM_CCMR1_IC2F_SHIFT)); ArCCMR2(timer) |= 0; ArCCER(timer) |= (ATIM_CCER_CC1E|ATIM_CCER_CC2E|ATIM_CCER_CC1P|ATIM_CCER_CC1NP|ATIM_CCER_CC2P|ATIM_CCER_CC2NP); ArDIER(timer) |= (ATIM_DIER_CC1IE|ATIM_DIER_CC2IE); break; } if(timer == 3) { /* generate an update event; reloads the counter, all registers */ ArEGR(timer) |= ATIM_EGR_UG ; /* enable the timer */ ArCR1(timer) |= GTIM_CR1_CEN; } else { /* generate an update event; reloads the counter, all registers */ rEGR(timer) |= GTIM_EGR_UG ; /* enable the timer */ rCR1(timer) |= GTIM_CR1_CEN; } }
static void input_pwm_timer_init(unsigned timer) { /* enable the timer clock before we try to talk to it */ modifyreg32(input_pwm_timers[timer].clock_register, 0, input_pwm_timers[timer].clock_bit); /* disable and configure the timer */ rCR1(timer) = 0; rCR2(timer) = 0; rSMCR(timer) = 0; rDIER(timer) = 0; rCCER(timer) = 0; rCCMR1(timer) = 0; rCCMR2(timer) = 0; rCCER(timer) = 0; rDCR(timer) = 0; /* claim our interrupt vector */ //irq_attach(input_pwm_timers[timer].irq_vector, input_pwm_tim_isr); // if ((input_pwm_timers[timer].base == STM32_TIM1_BASE) || (pwm_timers[timer].base == STM32_TIM8_BASE)) { // /* master output enable = on */ // rBDTR(timer) = ATIM_BDTR_MOE; // } /* configure the timer to free-run at 1MHz */ rPSC(timer) = (input_pwm_timers[timer].clock_freq / 1000000) - 1; /* run the full span of the counter */ rARR(timer) = 0xffff; /* generate an update event; reloads the counter, all registers */ rEGR(timer) = GTIM_EGR_UG; /* note that the timer is left disabled - arming is performed separately */ /* disable and configure the timer */ //rCR1 = 0; //rCR2 = 0; //rSMCR = 0; //rDIER = DIER_HRT | DIER_PPM; //rCCER = 0; /* unlock CCMR* registers */ //rCCMR1 = CCMR1_PPM; //rCCMR2 = CCMR2_PPM; //rCCER = CCER_PPM; //rDCR = 0; /* configure the timer to free-run at 1MHz */ //rPSC = (RC_TIMER_CLOCK / 1000000) - 1; /* this really only works for whole-MHz clocks */ /* set an initial capture a little ways off */ //rCCR_HRT = 1000; /* enable the timer and disable the update flag event */ rCR1(timer) = GTIM_CR1_UDIS | GTIM_CR1_CEN; /* enable interrupts */ //up_enable_irq(input_pwm_timers[timer].irq_vector); }