void radio_init(void)
{
TRACE_OUTS("radio_init\n");
//gpio_init(); done by spi_init at moment
spi_init(&radioConfig);
gpio_setout(RESET);
gpio_low(RESET);
gpio_setout(LED_RED);
gpio_low(LED_RED);
gpio_setout(LED_GREEN);
gpio_low(LED_GREEN);
TRACE_OUTS("reset...\n");
radio_reset();
TRACE_OUTS("reading radiover...\n");
uint8_t rv = radio_get_ver();
TRACE_OUTN(rv);
TRACE_NL();
if (rv < EXPECTED_RADIOVER) //TODO: make this ASSERT()
{
TRACE_OUTS("warning:unexpected radio ver<min\n");
//TRACE_FAIL("unexpected radio ver<min\n");
}
else if (rv > EXPECTED_RADIOVER)
{
TRACE_OUTS("warning:unexpected radio ver>exp\n");
}
radio_standby();
}
// *************************************************************************************************
// @fn open_radio
// @brief Prepare radio for RF communication.
// @param none
// @return none
// *************************************************************************************************
void open_radio(void)
{
// Reset radio core
radio_reset();
// Enable radio IRQ
RF1AIFG &= ~BIT4; // Clear a pending interrupt
RF1AIE |= BIT4; // Enable the interrupt
}
/**@brief Function for terminating the ongoing test (if any) and closing down the radio.
*/
static void dtm_test_done(void)
{
dtm_turn_off_test();
NRF_PPI->CHENCLR = 0x01;
NRF_PPI->CH[0].EEP = 0; // Break connection from timer to radio to stop transmit loop
NRF_PPI->CH[0].TEP = 0;
radio_reset();
m_state = STATE_IDLE;
}
// *************************************************************************************************
// @fn close_radio
// @brief Shutdown radio for RF communication.
// @param none
// @return none
// *************************************************************************************************
void close_radio(void)
{
// Disable radio IRQ
RF1AIFG = 0;
RF1AIE = 0;
// Reset radio core
radio_reset();
// Put radio to sleep
radio_powerdown();
}
void radio_init(void) {
// clear variables
memset(&radio_vars,0,sizeof(radio_vars_t));
// change state
radio_vars.state = RADIOSTATE_STOPPED;
// reset radio
radio_reset();
// change state
radio_vars.state = RADIOSTATE_RFOFF;
// start radiotimer with dummy setting to activate SFD pin interrupt
radiotimer_start(0xffff);
}
void radio_init() {
// clear variables
memset(&radio_vars, 0, sizeof(radio_vars_t));
// change state
radio_vars.state = RADIOSTATE_STOPPED;
// Set SCLK = 1 and SIMO = 0
PORT_PIN_SCLK_HIGH();
PORT_PIN_SIMO_LOW();
// Strobe CSn low/high
PORT_PIN_CS_LOW();
PORT_PIN_CS_HIGH();
// Hold CSn low and high for 40 microsec
PORT_PIN_CS_LOW();
delay(40);
PORT_PIN_CS_HIGH();
delay(40);
// Pull CSn low
PORT_PIN_CS_LOW();
// Wait for SOMI to go low
while (radio_vars.radioStatusByte.CHIP_RDYn != 0x00);
// reset radio
radio_reset();
// Wait until SOMI goes low again
while (radio_vars.radioStatusByte.CHIP_RDYn != 0x00);
// change state
radio_vars.state = RADIOSTATE_RFOFF;
// start radiotimer with dummy setting to activate SFD pin interrupt
radiotimer_start(0xffff);
}
/**@brief Function for initializing the radio for DTM.
*/
static uint32_t radio_init(void)
{
if(dtm_radio_validate(m_tx_power, m_radio_mode) != DTM_SUCCESS)
{
return DTM_ERROR_ILLEGAL_CONFIGURATION;
}
// Turn off radio before configuring it
radio_reset();
NRF_RADIO->TXPOWER = m_tx_power;
NRF_RADIO->MODE = m_radio_mode << RADIO_MODE_MODE_Pos;
// Set the access address, address0/prefix0 used for both Rx and Tx address
NRF_RADIO->PREFIX0 &= ~RADIO_PREFIX0_AP0_Msk;
NRF_RADIO->PREFIX0 |= (m_address >> 24) & RADIO_PREFIX0_AP0_Msk;
NRF_RADIO->BASE0 = m_address << 8;
NRF_RADIO->RXADDRESSES = RADIO_RXADDRESSES_ADDR0_Enabled << RADIO_RXADDRESSES_ADDR0_Pos;
NRF_RADIO->TXADDRESS = (0x00 << RADIO_TXADDRESS_TXADDRESS_Pos) & RADIO_TXADDRESS_TXADDRESS_Msk;
// Configure CRC calculation
NRF_RADIO->CRCCNF = (m_crcConfSkipAddr << RADIO_CRCCNF_SKIP_ADDR_Pos) |
(m_crcLength << RADIO_CRCCNF_LEN_Pos);
NRF_RADIO->PCNF0 = (m_packetHeaderS1len << RADIO_PCNF0_S1LEN_Pos) |
(m_packetHeaderS0len << RADIO_PCNF0_S0LEN_Pos) |
(m_packetHeaderLFlen << RADIO_PCNF0_LFLEN_Pos);
NRF_RADIO->PCNF1 = (m_whitening << RADIO_PCNF1_WHITEEN_Pos) |
(m_endian << RADIO_PCNF1_ENDIAN_Pos) |
(m_balen << RADIO_PCNF1_BALEN_Pos) |
(m_static_length << RADIO_PCNF1_STATLEN_Pos) |
(DTM_PAYLOAD_MAX_SIZE << RADIO_PCNF1_MAXLEN_Pos);
return DTM_SUCCESS;
}
// *************************************************************************************************
// @fn init_application
// @brief Initialize the microcontroller.
// @param none
// @return none
// *************************************************************************************************
void init_application(void)
{
volatile unsigned char *ptr;
#ifndef EMU
// ---------------------------------------------------------------------
// Enable watchdog
// Watchdog triggers after 16 seconds when not cleared
#ifdef USE_WATCHDOG
WDTCTL = WDTPW + WDTIS__512K + WDTSSEL__ACLK;
#else
WDTCTL = WDTPW + WDTHOLD;
#endif
// ---------------------------------------------------------------------
// Configure PMM
SetVCore(3);
// Set global high power request enable
PMMCTL0_H = 0xA5;
PMMCTL0_L |= PMMHPMRE;
PMMCTL0_H = 0x00;
// ---------------------------------------------------------------------
// Enable 32kHz ACLK
P5SEL |= 0x03; // Select XIN, XOUT on P5.0 and P5.1
UCSCTL6 &= ~XT1OFF; // XT1 On, Highest drive strength
UCSCTL6 |= XCAP_3; // Internal load cap
UCSCTL3 = SELA__XT1CLK; // Select XT1 as FLL reference
UCSCTL4 = SELA__XT1CLK | SELS__DCOCLKDIV | SELM__DCOCLKDIV;
// ---------------------------------------------------------------------
// Configure CPU clock for 12MHz
_BIS_SR(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select suitable range
UCSCTL2 = FLLD_1 + 0x16E; // Set DCO Multiplier
_BIC_SR(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
__delay_cycles(250000);
// Loop until XT1 & DCO stabilizes, use do-while to insure that
// body is executed at least once
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
SFRIFG1 &= ~OFIFG; // Clear fault flags
} while ((SFRIFG1 & OFIFG));
// ---------------------------------------------------------------------
// Configure port mapping
// Disable all interrupts
__disable_interrupt();
// Get write-access to port mapping registers:
PMAPPWD = 0x02D52;
// Allow reconfiguration during runtime:
PMAPCTL = PMAPRECFG;
// P2.7 = TA0CCR1A or TA1CCR0A output (buzzer output)
ptr = &P2MAP0;
*(ptr+7) = PM_TA1CCR0A;
P2OUT &= ~BIT7;
P2DIR |= BIT7;
// P1.5 = SPI MISO input
ptr = &P1MAP0;
*(ptr+5) = PM_UCA0SOMI;
// P1.6 = SPI MOSI output
*(ptr+6) = PM_UCA0SIMO;
// P1.7 = SPI CLK output
*(ptr+7) = PM_UCA0CLK;
// Disable write-access to port mapping registers:
PMAPPWD = 0;
// Re-enable all interrupts
__enable_interrupt();
#endif
// ---------------------------------------------------------------------
// Configure ports
// ---------------------------------------------------------------------
// Reset radio core
radio_reset();
radio_powerdown();
// ---------------------------------------------------------------------
// Init acceleration sensor
as_init();
// ---------------------------------------------------------------------
// Init LCD
lcd_init();
// ---------------------------------------------------------------------
// Init buttons
init_buttons();
// ---------------------------------------------------------------------
// Configure Timer0 for use by the clock and delay functions
Timer0_Init();
// ---------------------------------------------------------------------
// Init pressure sensor
ps_init();
}
int main(int argc, char *argv[])
{
FILE *fp_load;
int fd_pcie;
int ret = 0,via_fpga = 0;
int fd_spi,fd_fpga;
unsigned int jdma_handle;
char jdma_tx_status;
char jdma_rx_status;
int fd_rad;
int i,j;
char do_what;
double central_freq_point;
int exit_flag = 0;
unsigned int rx_data_size = 0;
ADRADPROFILE load_data[5000];
unsigned int write_tm_reg[2];
char input_str1[10];
char input_str2[10];
unsigned int write_syncnet_reg[2];
char s[80];
unsigned long pcie_data,data;
char pcie_data_back[4];
JDMAREGS jdmaregs;
JESDREGS jesdregs;
RADTMREGS radtmregs;
IQCONFIG IqCntCfg;
SYNCNET_CONFIG syncnet_regs;
parse_opts(argc, argv);
if (RadId != 0 && RadId != 1)
pabort("Invalid RadId ID. Use 0 for CMOS, 1 for LVDS radio");
RadConfig.RadId = RadId;
if (type_cluster != 0 && type_cluster != 1)
pabort("Invalid type_cluster ID. Use 0 for Master, 1 for Slave Cluster");
RadConfig.TypeCluster = type_cluster;
if (agc_or_mgc != 0 && agc_or_mgc != 1)
pabort("Invalid agc_or_mgc ID. Use 0 for AGC, 1 for MGC");
if (RadConfig.NumAntennas != 1 && RadConfig.NumAntennas != 2)
pabort("Invalid number of antennas. Use 1 or 2");
if (radio_mode == -1) {
radio_mode = (RadId == 0) ? RADMODE_LEVEL : RADMODE_PULSE; // set Level mode as default for CMOS and Pulse as default for LVDS
printf("RadId=%d radio_mode=%d\n", RadId, radio_mode);
}
RadConfig.RadioMode = radio_mode;
if (radio_band == -1)
radio_band = (RadId == 0) ? 2 : 7; // set Band 2 as default for CMOS and Band 7 as default for LVDS
RadConfig.Band = radio_band;
if (radio_sampling_rate == -1)
radio_sampling_rate = (RadId == 0) ? SAMPLING_RATE_5MHZ : SAMPLING_RATE_10MHZ; // set 7680 as default for CMOS and 15360 as default for LVDS
else {
if (radio_sampling_rate != SAMPLING_RATE_5MHZ && radio_sampling_rate != SAMPLING_RATE_10MHZ && radio_sampling_rate != SAMPLING_RATE_20MHZ)
pabort("Invalid smpling rate. Supports only 7680, 15360 and 30720");
}
RadConfig.SamplingRate = radio_sampling_rate;
if (radio_loopback == 0) {
RadConfig.TxLoopback = 0;
}
else if (radio_loopback == 1)
RadConfig.TxLoopback = 1;
else
pabort("Invalid radio loopback mode. Supports only 0-no loopback, 1-Tx loopback ");
fd_spi = open(spi_device[RadId], O_RDWR);
if (fd_spi < 0) {
printf("Can't open %s RadId. ", spi_device[RadId]);
abort();
}
fd_fpga = open("/dev/fpga", O_RDWR);
if(fd_fpga < 0) {
printf("Cannot Open /dev/fpga.\n");
// abort();
}
if (radio_init) {
printf("Setting up radio 1 using Band7 %d Mhz LTE LVDS profile", (SAMPLING_RATE_20MHZ==radio_sampling_rate)? 20:((SAMPLING_RATE_10MHZ==radio_sampling_rate)? 10:5));
printf("\n%s Mode, NumAntennas=%d, TxLoopback=%d, %s Mode\n", (radio_mode == RADMODE_LEVEL) ? "Level" : "Pulse", RadConfig.NumAntennas, RadConfig.TxLoopback, (0 == agc_or_mgc)?"AGC":"MGC");
#if 1
spi_config(fd_spi);
#endif
if (radio_reset_request)
radio_reset();
}
if (radio_test_time) {
fd_rad = open(rad_device[RadId], O_RDWR);
ret = ioctl(fd_rad,TRAD_IOCTL_INIT_SYS ,NULL);
if (fd_rad < 0) {
printf("Can't open %s RadId. ", rad_device[RadId]);
abort();
}
if(0 == type_cluster) //only master init 9361
{
printf("Initializing AD9361 ...\n");
if (0 == agc_or_mgc)
{
if(SAMPLING_RATE_20MHZ == radio_sampling_rate) {
if ((fp_load = fopen(".load_20BW_2555_lvds_AGC","a+")) == NULL) {
printf("open fail\n");
exit(1);
}
}
else if(SAMPLING_RATE_10MHZ == radio_sampling_rate) {
if ((fp_load = fopen(".load_10BW_2555_lvds_AGC","a+")) == NULL) {
printf("open fail\n");
exit(1);
}
}
else if(SAMPLING_RATE_5MHZ == radio_sampling_rate) {
if ((fp_load = fopen(".load_5BW_2555_lvds_AGC","a+")) == NULL) {
printf("open fail\n");
exit(1);
}
}
}
else if (1 == agc_or_mgc)
{
if(SAMPLING_RATE_20MHZ == radio_sampling_rate) {
if ((fp_load = fopen(".load_20BW_2555_lvds_MGC","a+")) == NULL) {
printf("open fail\n");
exit(1);
}
}
else if(SAMPLING_RATE_10MHZ == radio_sampling_rate) {
if ((fp_load = fopen(".load_10BW_2555_lvds_MGC","a+")) == NULL) {
printf("open fail\n");
exit(1);
}
}
else if(SAMPLING_RATE_5MHZ == radio_sampling_rate) {
if ((fp_load = fopen(".load_5BW_2555_lvds_MGC","a+")) == NULL) {
printf("open fail\n");
exit(1);
}
}
}
i = 0;
while (fscanf(fp_load,"%u %u %u",&load_data[i].OpCode,&load_data[i].Addr,&load_data[i].Data) > 0) {
i++;
};
RadConfig.pRadProfile = (PADRADPROFILE)load_data;
if(0xa == Ad9361ReadReg(0, fd_spi, 0x37))
{
via_fpga = 0;
lseek(fd_fpga, 0x20, SEEK_SET);
data = 0x0;
usleep(1);
write(fd_fpga, &data, 1);
printf("Coinfig AD9361 via SPI\n");
}
else if(0xa == Ad9361ReadReg(1, fd_fpga, 0x37))
{
via_fpga = 1;
fd_spi = fd_fpga;
printf("Coinfig AD9361 via FPGA\n");
}
else
{
printf("Config AD9361 ERROR!!!\tSPI failed FPGA failed\n");
return 1;
}
Ad9361RadioInit(via_fpga, fd_spi, &RadConfig);
if (radio_mode == RADMODE_LEVEL)
Ad9361WriteReg(via_fpga, fd_spi, 0x14, 0x23); // for level mode move radio to FDD active state
else
Ad9361WriteReg(via_fpga, fd_spi, 0x14, 0x13); // for pulse mode enable pin control
fclose(fp_load);
}
#ifdef PCIE
fd_pcie = open("/dev/pciedrv", O_RDWR);
if (fd_pcie < 0) {
printf("Can't open /dev/pciedrv.\n");
abort();
}
printf("fd_pcie is %d\n",fd_pcie);
if(0 == type_cluster)
{
pcie_data = 0xd0;
write(fd_pcie, &pcie_data, sizeof(pcie_data));
printf("Init 9361 OK.\nMaster writing 0xd0 to PCIe ADDR. 0x0\n");
}
else
{
pcie_data_back[0] = 0;
printf("Waiting Master init 9361, and reading PCIe to make sure\n");
//while(pcie_data != 0xd0)
{
read(fd_pcie, pcie_data_back, sizeof(pcie_data));
printf("%d ",pcie_data_back[0]);
usleep(1000);
}
printf("Slave read 0xd0 from PCIe ADDR. 0x0\nInit 9361 OK.\n");
}
close(fd_pcie);
#endif
printf("This %s Cluster, config & enable\n", (RadConfig.TypeCluster==0) ? "Master":"Slave");
ret = ioctl(fd_rad, TRAD_IOCTL_SET_RAD_CONFIG, &RadConfig);
if (ret)
pabort("Radio Config IOCTL failed");
else
printf("%s Radio Config OK\n", (RadConfig.TypeCluster==0) ? "Master":"Slave");
ret = ioctl(fd_rad, TRAD_IOCTL_ENABLE, 0);
if (ret)
printf("Radio enable fails.\n");
else
printf("%s Radio Enable OK\n", (RadConfig.TypeCluster==0) ? "Master":"Slave");
/*
* 9361自发数据
Ad9361WriteReg(fd_spi, 0x14, 0x23);
Ad9361WriteReg(fd_spi, 0x3f4, 0x0b);
*/
close(fd_rad);
}
close(fd_spi);
close(fd_fpga);
return ret;
}
void init_application(void)
{
volatile unsigned char *ptr;
// ---------------------------------------------------------------------
// Enable watchdog
// Watchdog triggers after 16 seconds when not cleared
#ifdef USE_WATCHDOG
WDTCTL = WDTPW + WDTIS__512K + WDTSSEL__ACLK;
#else
WDTCTL = WDTPW + WDTHOLD;
#endif
// ---------------------------------------------------------------------
// Configure port mapping
// Disable all interrupts
__disable_interrupt();
// Get write-access to port mapping registers:
PMAPPWD = 0x02D52;
// Allow reconfiguration during runtime:
PMAPCTL = PMAPRECFG;
// P2.7 = TA0CCR1A or TA1CCR0A output (buzzer output)
ptr = &P2MAP0;
*(ptr + 7) = PM_TA1CCR0A;
P2OUT &= ~BIT7;
P2DIR |= BIT7;
// P1.5 = SPI MISO input
ptr = &P1MAP0;
*(ptr + 5) = PM_UCA0SOMI;
// P1.6 = SPI MOSI output
*(ptr + 6) = PM_UCA0SIMO;
// P1.7 = SPI CLK output
*(ptr + 7) = PM_UCA0CLK;
// Disable write-access to port mapping registers:
PMAPPWD = 0;
// Re-enable all interrupts
__enable_interrupt();
// Init the hardwre real time clock (RTC_A)
rtca_init();
// ---------------------------------------------------------------------
// Configure ports
// ---------------------------------------------------------------------
// Reset radio core
radio_reset();
radio_powerdown();
#ifdef CONFIG_ACCELEROMETER
// ---------------------------------------------------------------------
// Init acceleration sensor
as_init();
#else
as_disconnect();
#endif
// ---------------------------------------------------------------------
// Init buttons
init_buttons();
// ---------------------------------------------------------------------
// Configure Timer0 for use by the clock and delay functions
timer0_init();
/* Init buzzer */
buzzer_init();
// ---------------------------------------------------------------------
// Init pressure sensor
ps_init();
/* drivers/battery */
battery_init();
/* drivers/temperature */
temperature_init();
#ifdef CONFIG_INFOMEM
if (infomem_ready() == -2) {
infomem_init(INFOMEM_C, INFOMEM_C + 2 * INFOMEM_SEGMENT_SIZE);
}
#endif
}