int main(void)
{
/* Enable HSE */
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
/* setup PLL */
// 8Mhz *8/2 -> 32MHz
rcc_set_pll_source(RCC_HSE);
rcc_set_pll_multiplier(RCC_CFGR_PLLMUL_MUL8);
rcc_set_pll_divider(RCC_CFGR_PLLDIV_DIV2);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* switch to PLL */
rcc_set_sysclk_source(RCC_PLL);
/* setup AHB/APBx */
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
rcc_set_ppre1(RCC_CFGR_PPRE1_NODIV);
rcc_set_ppre2(RCC_CFGR_PPRE2_NODIV);
gpio_setup();
systick_setup(2);
/* init switch */
gpio_mode_setup(GPIOA, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, GPIO12);
gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO11);
gpio_clear(GPIOA, GPIO11);
/* get value */
gpio_get(GPIOA, GPIO12);
while (1) {
/*
delay();
gpio_toggle(LED_GREEN_PORT, LED_GREEN_PIN);
delay_short();
gpio_toggle(LED_GREEN_PORT, LED_GREEN_PIN);
delay_short();
gpio_toggle(LED_GREEN_PORT, LED_GREEN_PIN);
delay_short();
gpio_toggle(LED_GREEN_PORT, LED_GREEN_PIN);
delay_short();
*/
}
return 0;
}
/* Set the clock to max speed. */
static void clock_setup(void)
{
#if defined(STM32F0)
rcc_clock_setup_in_hsi_out_48mhz();
#elif defined(STM32L0)
/* After a reset, the system uses [email protected]. */
/* end result: 32MHz PLLVCO from HSI16,
* no system/periph clock divide.
*/
/* increase the latency to 1 wait state (we'll be speeding up) */
flash_set_ws(1);
/* turn on HSI16 */
rcc_osc_on(RCC_HSI16);
rcc_wait_for_osc_ready(RCC_HSI16);
/* run AHB, APB1, APB2 at full speed */
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
rcc_set_ppre1(RCC_CFGR_PPRE1_NODIV);
rcc_set_ppre2(RCC_CFGR_PPRE2_NODIV);
/* turn off PLL and wait for it to fully stop */
rcc_osc_off(RCC_PLL);
while (RCC_CR & RCC_CR_PLLRDY);
/* set PLL source to HSI16 */
RCC_CFGR &= ~(1<<16); // RCC_CFGR_PLLSRC
/* set up PLL */
rcc_set_pll_multiplier(RCC_CFGR_PLLMUL_MUL4);
rcc_set_pll_divider(RCC_CFGR_PLLDIV_DIV2);
/* turn on and switch to PLL */
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
rcc_set_sysclk_source(RCC_PLL);
rcc_ahb_frequency = 32000000;
rcc_apb1_frequency = 32000000;
rcc_apb2_frequency = 32000000;
#else
#error "Implement a clock setup."
#endif
}
void clock_init(void) {
/* Enable HSE */
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
/* setup PLL */
// 8Mhz *8/2 -> 32MHz
rcc_set_pll_source(RCC_HSE);
rcc_set_pll_multiplier(RCC_CFGR_PLLMUL_MUL8);
rcc_set_pll_divider(RCC_CFGR_PLLDIV_DIV2);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* switch to PLL */
rcc_set_sysclk_source(RCC_PLL);
/* setup AHB/APBx */
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
rcc_set_ppre1(RCC_CFGR_PPRE1_NODIV);
rcc_set_ppre2(RCC_CFGR_PPRE2_NODIV);
}
/**
* Set up sysclock with PLL from HSI16
* @param clock full struct with desired parameters
*/
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
{
/* Turn on the appropriate source for the PLL */
if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) {
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
} else {
rcc_osc_on(RCC_HSI16);
rcc_wait_for_osc_ready(RCC_HSI16);
}
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
rcc_periph_clock_enable(RCC_PWR);
pwr_set_vos_scale(clock->voltage_scale);
rcc_osc_off(RCC_PLL);
while (rcc_is_osc_ready(RCC_PLL));
flash_prefetch_enable();
flash_set_ws(clock->flash_waitstates);
/* Set up the PLL */
rcc_set_pll_multiplier(clock->pll_mul);
rcc_set_pll_divider(clock->pll_div);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
rcc_set_sysclk_source(RCC_PLL);
/* Set the peripheral clock frequencies used. */
rcc_ahb_frequency = clock->ahb_frequency;
rcc_apb1_frequency = clock->apb1_frequency;
rcc_apb2_frequency = clock->apb2_frequency;
}
