static void setupClocks(void) { rcc_clk_init(RCC_CLKSRC_PLL, RCC_PLLSRC_HSE, RCC_PLLMUL_9); rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1); rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_2); rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_1); }
__weak void board_setup_clock_prescalers(void) { rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1); rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_2); rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_1); rcc_clk_disable(RCC_USB); #if F_CPU == 72000000 rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5); #elif F_CPU == 48000000 rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1); #endif }
void adc_init(void) { rcc_set_prescaler(RCC_PRESCALER_ADC, RCC_ADCPRE_PCLK_DIV_6); rcc_clk_enable(RCC_ADC1); rcc_reset_dev(RCC_ADC1); ADC_CR1 = 0; ADC_CR2 = CR2_EXTSEL_SWSTART | CR2_EXTTRIG; // Software triggers conversions ADC_SQR1 = 0; /* Up the sample conversion time to 55.5 cycles/sec, see note above */ /* TODO: fix magic numbers */ ADC_SMPR1 = 0xB6DB6D; ADC_SMPR2 = 0x2DB6DB6D; /* Enable the ADC */ CR2_ADON_BIT = 1; /* Reset the calibration registers and then perform a reset */ CR2_RSTCAL_BIT = 1; while(CR2_RSTCAL_BIT) ; CR2_CAL_BIT = 1; while(CR2_CAL_BIT) ; }
/* * Clock setup. Note that some of this only takes effect if we're * running bare metal and the bootloader hasn't done it for us * already. * * If you change this function, you MUST change the file-level Doxygen * comment above. */ static void setupClocks() { #if defined(BOARD_STBee) rcc_clk_init(RCC_CLKSRC_PLL, RCC_PLLSRC_HSE, RCC_PLLMUL_6); // for 12Mhz board (STBee) #elif defined(BOARD_STBee2) rcc_clk_init(RCC_CLKSRC_PLL, RCC_PLLSRC_HSE, RCC_PLLMUL_6); // for 12Mhz board (STBee with init SRAM) #elif defined(BOARD_STBeeMini) rcc_clk_init(RCC_CLKSRC_PLL, RCC_PLLSRC_HSE, RCC_PLLMUL_6); // for 12Mhz board (STBeeMini) #elif defined(BOARD_STM32VLD) rcc_clk_init(RCC_CLKSRC_PLL, RCC_PLLSRC_HSE, RCC_PLLMUL_3); // 24Mhz = 8Mhz x3 (STM32VLD) #else rcc_clk_init(RCC_CLKSRC_PLL, RCC_PLLSRC_HSE, RCC_PLLMUL_9); #endif rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1); rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_2); rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_1); }
static void setup_clocks(void) { // Turn on HSI. We'll switch to and run off of this while we're // setting up the main PLL. rcc_turn_on_clk(RCC_CLK_HSI); // Turn off and reset the clock subsystems we'll be using, as well // as the clock security subsystem (CSS). Note that resetting CFGR // to its default value of 0 implies a switch to HSI for SYSCLK. RCC_BASE->CFGR = 0x00000000; rcc_disable_css(); rcc_turn_off_clk(RCC_CLK_PLL); rcc_turn_off_clk(RCC_CLK_HSE); //Removed board_reset_pll(void) because it's not implemented // Clear clock readiness interrupt flags and turn off clock // readiness interrupts. RCC_BASE->CIR = 0x00000000; // Enable HSE, and wait until it's ready. rcc_turn_on_clk(RCC_CLK_HSE); while (!rcc_is_clk_ready(RCC_CLK_HSE)) ; // Configure AHBx, APBx, etc. prescalers and the main PLL. //wirish::priv::board_setup_clock_prescalers(); rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1); rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_2); rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_1); rcc_configure_pll(&w_board_pll_cfg); // Enable the PLL, and wait until it's ready. rcc_turn_on_clk(RCC_CLK_PLL); while(!rcc_is_clk_ready(RCC_CLK_PLL)) ; // Finally, switch to the now-ready PLL as the main clock source. rcc_switch_sysclk(RCC_CLKSRC_PLL); }
void adc_set_prescaler(adc_prescaler pre) { rcc_set_prescaler(RCC_PRESCALER_ADC, (uint32)pre); }
__weak void board_setup_clock_prescalers(void) { rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1); rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_2); rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_1); }
static void setupADC() { rcc_set_prescaler(RCC_PRESCALER_ADC, RCC_ADCPRE_PCLK_DIV_6); adc_foreach(adcDefaultConfig); }