/** Read all core registers
*
* @note
* commandBuffer\n
* - [2] => flag - must be zero
* - [3] => register index to start at
* - [4] => register index to end at
*
* @return
* == \ref BDM_RC_OK => success \n
* \n
* commandBuffer \n
* - [1..N] => 32-bit register values
*/
uint8_t f_CMD_SWD_READ_ALL_CORE_REGS(void) {
uint8_t rc;
uint8_t regIndex = commandBuffer[3];
uint8_t endRegister = commandBuffer[4];
uint8_t* outputPtr = commandBuffer+1;
uint8_t command[4];
returnSize = 1;
if (commandBuffer[2] != 0) {
// Check flag is zero
return BDM_RC_ILLEGAL_PARAMS;
}
while (regIndex<=endRegister) {
rc = readCoreRegister(regIndexMap[regIndex], command);
if (rc != BDM_RC_OK) {
return rc;
}
// Write to buffer (target format - Little-endian ARM)
*outputPtr++ = command[3];
*outputPtr++ = command[2];
*outputPtr++ = command[1];
*outputPtr++ = command[0];
returnSize += 4;
regIndex++;
}
return BDM_RC_OK;
}
void xtest_datawatchpoint_TestCase_DoubleWrite()
{
uint32_t pc = 0 ;
uint32_t r1 = 0 ;
setDataWatchpoint_MatchingOneComparator(COMPARATOR_0,0x2000045C,WATCHPOINT_MASK_NOTHING,0xA,WATCHPOINT_WORD,WATCHPOINT_WRITE);
writeCoreRegister(CORE_REG_PC,0x080009D0);
setCoreMode(CORE_DEBUG_MODE);
while(!hasDWTTrapDebugEventOccured());
pc = readCoreRegister(CORE_REG_PC);
r1 = readCoreRegister(CORE_REG_R1);
// TEST_ASSERT_EQUAL(,pc);
}
void test_datawatchpoint_TestCase_ReadByte_LDRB()
{
uint32_t pc = 0 ;
writeCoreRegister(CORE_REG_PC,0x080003F0);
setDataWatchpoint_MatchingOneComparator(COMPARATOR_0,0x2000045C,WATCHPOINT_MASK_NOTHING,0x11223344,WATCHPOINT_BYTE,WATCHPOINT_READ);
setCoreMode(CORE_DEBUG_MODE);
pc = readCoreRegister(CORE_REG_PC);
// TEST_ASSERT_EQUAL(0x080003FC,pc);
}
void xtest_datawatchpoint_TestCase_ReadByte_LDR()
{
uint32_t pc = 0 ;
setDataWatchpoint_MatchingOneComparator(COMPARATOR_0,0x2000045C,WATCHPOINT_MASK_NOTHING,0x44,WATCHPOINT_BYTE,WATCHPOINT_READ);
writeCoreRegister(CORE_REG_PC,0x080005F0);
setCoreMode(CORE_DEBUG_MODE);
while(!hasDWTTrapDebugEventOccured());
pc = readCoreRegister(CORE_REG_PC);
// TEST_ASSERT_EQUAL(,pc);
}
/** Read ARM-SWD core register
*
* @note
* commandBuffer\n
* - [2..3] => 16-bit register number [MSB ignored]
*
* @return
* == \ref BDM_RC_OK => success \n
* \n
* commandBuffer \n
* - [1..4] => 32-bit register value
*/
uint8_t f_CMD_SWD_READ_REG(void) {
returnSize = 5;
return readCoreRegister(commandBuffer[3], commandBuffer+1);
}
