static void wait_ready()
{
uint8_t fsr = read_fsr();
// wait flash ready flag
while (fsr & FSR_RDYN)
fsr = read_fsr();
}
static void disable_infen()
{
uint8_t fsr = read_fsr();
// if INFEN is enabled, try to disable it
if (fsr & FSR_INFEN) {
write_fsr(fsr & ~FSR_INFEN);
fsr = read_fsr();
if (fsr & FSR_INFEN) {
fprintf(stderr, "failed to unset INFEN bit on FSR\n");
exit(EXIT_FAILURE);
}
}
}
static void enable_infen()
{
uint8_t fsr = read_fsr();
// if INFEN is not enabled, try to enable it
if (!(fsr & FSR_INFEN)) {
write_fsr(fsr | FSR_INFEN);
fsr = read_fsr();
if (!(fsr & FSR_INFEN)) {
fprintf(stderr, "failed to set INFEN bit on FSR\n");
exit(EXIT_FAILURE);
}
}
}
static int spi_nor_wait_till_fsr_ready(struct spi_nor *nor)
{
unsigned long deadline;
int sr;
int fsr;
deadline = jiffies + MAX_READY_WAIT_JIFFIES;
do {
cond_resched();
sr = read_sr(nor);
if (sr < 0) {
break;
} else if (!(sr & SR_WIP)) {
fsr = read_fsr(nor);
if (fsr < 0)
break;
if (fsr & FSR_READY)
return 0;
}
} while (!time_after_eq(jiffies, deadline));
return -ETIMEDOUT;
}
static void enable_wen()
{
uint8_t fsr = read_fsr();
uint8_t cmd[1];
// if WEN is not enabled, try to enable it
if (!(fsr & FSR_WEN)) {
cmd[0] = WREN;
spi_transfer(cmd, sizeof(cmd));
fsr = read_fsr();
if (!(fsr & FSR_WEN)) {
fprintf(stderr, "failed to set WEN bit on FSR\n");
exit(EXIT_FAILURE);
}
}
}
static inline int spi_nor_fsr_ready(struct spi_nor *nor)
{
int fsr = read_fsr(nor);
if (fsr < 0)
return fsr;
else
return fsr & FSR_READY;
}
static void cmd_read_fsr()
{
uint8_t fsr;
fsr = read_fsr();
printf("status register (FSR): 0x%02x\n", fsr);
printf("ENDEBUG is%s set\n", (fsr & FSR_ENDEBUG) ? "" : " not");
printf("STP is%s set\n", (fsr & FSR_STP) ? "" : " not");
printf("WEN is%s set\n", (fsr & FSR_WEN) ? "" : " not");
printf("RDYN is%s set\n", (fsr & FSR_RDYN) ? "" : " not");
printf("INFEN is%s set\n", (fsr & FSR_INFEN) ? "" : " not");
printf("RDISMB is%s set\n", (fsr & FSR_RDISMB) ? "" : " not");
}
static int check_rdismb()
{
return (read_fsr() & FSR_RDISMB) ? 1 : 0;
}
