/* Send "write enable" command to SPI flash chip. */
static int lpcspifi_write_enable(struct flash_bank *bank)
{
struct target *target = bank->target;
struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
uint32_t ssp_base = lpcspifi_info->ssp_base;
uint32_t io_base = lpcspifi_info->io_base;
uint32_t status, value;
int retval = ERROR_OK;
retval = ssp_setcs(target, io_base, 0);
if (retval == ERROR_OK)
retval = ssp_write_reg(target, ssp_base, SSP_DATA, SPIFLASH_WRITE_ENABLE);
if (retval == ERROR_OK)
retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
if (retval == ERROR_OK)
retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
if (retval == ERROR_OK)
retval = ssp_setcs(target, io_base, 1);
/* read flash status register */
if (retval == ERROR_OK)
retval = read_status_reg(bank, &status);
if (retval != ERROR_OK)
return retval;
/* Check write enabled */
if ((status & SPIFLASH_WE_BIT) == 0) {
LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
return ERROR_FAIL;
}
return retval;
}
/* Send "write enable" command to SPI flash chip. */
static int ath79_write_enable(struct flash_bank *bank)
{
uint32_t status;
int retval;
uint8_t spi_bytes[] = {SPIFLASH_WRITE_ENABLE};
/* Send SPI command "write enable" */
ath79_spi_bitbang_prepare(bank);
retval = ath79_spi_bitbang_bytes(
bank, spi_bytes, sizeof(spi_bytes),
ATH79_XFER_FINAL);
if (retval != ERROR_OK)
return retval;
/* read flash status register */
retval = read_status_reg(bank, &status);
if (retval != ERROR_OK)
return retval;
/* Check write enabled */
if ((status & SPIFLASH_WE_BIT) == 0) {
LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32,
status);
return ERROR_FAIL;
}
return ERROR_OK;
}
/* Send "write enable" command to SPI flash chip.
* The operation is triggered by setting SMI_WE bit, and SMI sends
* the proper SPI command (0x06) */
static int smi_write_enable(struct flash_bank *bank)
{
struct target *target = bank->target;
struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
uint32_t io_base = stmsmi_info->io_base;
uint32_t status;
int retval;
/* Enter in HW mode */
SMI_SET_HW_MODE(); /* AB: is this correct ?*/
/* clear transmit finished flag */
SMI_CLEAR_TFF();
/* Send write enable command */
SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_WE);
/* Poll transmit finished flag */
SMI_POLL_TFF(SMI_CMD_TIMEOUT);
/* read flash status register */
retval = read_status_reg(bank, &status);
if (retval != ERROR_OK)
return retval;
/* Check write enabled */
if ((status & SMI_WEL_BIT) == 0)
{
LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
return ERROR_FAIL;
}
return ERROR_OK;
}
void wait_cgp(fitness_t *fitarr, u32 *frames)
{
int i;
u32 stat_reg;
do {
stat_reg = read_status_reg();
} while ((stat_reg & STAT_END_MASK) != STAT_END_MASK);
*frames = (stat_reg & STAT_FRAME_MASK) >> STAT_FRAME_SHIFT;
for (i = 0; i < CGP_INDIVS; ++i)
fitarr[i] = Xil_In32(get_fitness_reg(i));
}
void write_memory_code(u16 addr, u8 *buf, u16 length)
{
if ((read_status_reg() & 0x02) == 0)
{
set_write_enable_latch();
}
FRAM_CS_LOW();
FRAMReadWriteByte(0x02);
FRAMReadWriteByte((u8)(addr/256));
FRAMReadWriteByte((u8)(addr%256));
for (u16 i = 0; i < length; i++)
{
FRAMReadWriteByte(buf[i]);
}
FRAM_CS_HIGH();
reset_write_enable_latch();
}
/* timeout in ms */
static int wait_till_ready(struct flash_bank *bank, int timeout)
{
uint32_t status;
int retval;
long long endtime;
endtime = timeval_ms() + timeout;
do {
/* read flash status register */
retval = read_status_reg(bank, &status);
if (retval != ERROR_OK)
return retval;
if ((status & SPIFLASH_BSY_BIT) == 0)
return ERROR_OK;
alive_sleep(1);
} while (timeval_ms() < endtime);
LOG_ERROR("timeout");
return ERROR_FAIL;
}
static unsigned
mn103ser_io_read_buffer (struct hw *me,
void *dest,
int space,
unsigned_word base,
unsigned nr_bytes)
{
struct mn103ser *serial = hw_data (me);
enum serial_register_types serial_reg;
HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
serial_reg = decode_addr (me, serial, base);
switch (serial_reg)
{
/* control registers */
case SC0CTR:
case SC1CTR:
case SC2CTR:
read_control_reg(me, serial, serial_reg-SC0CTR, dest, nr_bytes);
HW_TRACE ((me, "read - ctrl reg%d has 0x%x\n", serial_reg-SC0CTR,
*(unsigned8 *)dest));
break;
/* interrupt mode registers */
case SC0ICR:
case SC1ICR:
case SC2ICR:
read_intmode_reg(me, serial, serial_reg-SC0ICR, dest, nr_bytes);
HW_TRACE ((me, "read - intmode reg%d has 0x%x\n", serial_reg-SC0ICR,
*(unsigned8 *)dest));
break;
/* transmission buffers */
case SC0TXB:
case SC1TXB:
case SC2TXB:
read_txb(me, serial, serial_reg-SC0TXB, dest, nr_bytes);
HW_TRACE ((me, "read - txb%d has %c\n", serial_reg-SC0TXB,
*(char *)dest));
break;
/* reception buffers */
case SC0RXB:
case SC1RXB:
case SC2RXB:
read_rxb(me, serial, serial_reg-SC0RXB, dest, nr_bytes);
HW_TRACE ((me, "read - rxb%d has %c\n", serial_reg-SC0RXB,
*(char *)dest));
break;
/* status registers */
case SC0STR:
case SC1STR:
case SC2STR:
read_status_reg(me, serial, serial_reg-SC0STR, dest, nr_bytes);
HW_TRACE ((me, "read - status reg%d has 0x%x\n", serial_reg-SC0STR,
*(unsigned8 *)dest));
break;
case SC2TIM:
read_serial2_timer_reg(me, serial, dest, nr_bytes);
HW_TRACE ((me, "read - serial2 timer reg %d\n", *(unsigned8 *)dest));
break;
default:
hw_abort(me, "invalid address");
}
return nr_bytes;
}
int fifo_write_error()
{
return ((read_status_reg() & STAT_WRERR_MASK) == STAT_WRERR_MASK);
}
int fifo_read_error()
{
return ((read_status_reg() & STAT_RDERR_MASK) == STAT_RDERR_MASK);
}
u32 read_frame_number()
{
return (read_status_reg() & STAT_FRAME_MASK) >> STAT_FRAME_SHIFT;
}
uint16_t flash_reprogram(uint16_t handle) {
// Determine file size.
uint32_t data_size = file_size(handle);
// Check device ID.
uint32_t id = read_device_id();
printf("ID: 0x%08lx\n", id);
if (id != EXPECTED_DEVICE_ID) {
return FLASH_PROGRAM_ID_MISMATCH;
}
// Erase enough sectors to fit the new configuration file.
#if defined(DEBUG)
printf_P(PSTR("Erasing chip\n"));
#endif // defined (DEBUG)
// Set write enable.
write_enable();
// Start block erase.
chip_erase();
// Make sure WIP bit is set.
if (!(read_status_reg() & (1 << STATUS_REG_WIP))) {
return FLASH_PROGRAM_ERASE_START_ERROR;
}
// Wait for WIP = 0.
// TODO: add timeout.
while (read_status_reg() & (1 << STATUS_REG_WIP));
// Write the new data to flash.
char file_buf[PAGE_SIZE];
for (uint32_t offset = 0; offset < data_size; offset += PAGE_SIZE) {
// Read the file.
uint16_t size_read = file_read(handle, file_buf, PAGE_SIZE);
if (size_read < PAGE_SIZE && size_read != offset - data_size) {
return FLASH_PROGRAM_FILE_READ_ERROR;
}
bool page_empty = true;
for (uint16_t page_offset = 0; page_offset < size_read; ++page_offset) {
if (file_buf[page_offset] != UNINITIALIZED_MEMORY_VALUE) {
page_empty = false;
break;
}
}
if (page_empty) {
#if defined(DEBUG)
printf_P(PSTR("No data at 0x%08lx\n"), offset);
#endif // defined(DEBUG)
continue;
}
// Obtain a 32-bit checksum.
uint32_t checksum = get_checksum(file_buf, size_read);
// Program a |PAGE_SIZE| page of the flash.
write_enable();
#if defined(DEBUG)
printf_P(PSTR("Programming data at 0x%08lx\n"), offset);
#endif // defined(DEBUG)
page_program(offset, file_buf, size_read);
// Make sure WIP bit is set.
if (!(read_status_reg() & (1 << STATUS_REG_WIP))) {
return FLASH_PROGRAM_WRITE_START_ERROR;
}
// Wait for programming to finish.
// TODO: add timeout.
while (read_status_reg() & (1 << STATUS_REG_WIP));
// Read back and check the checksum.
read_data(offset, file_buf, size_read);
uint32_t new_checksum = get_checksum(file_buf, size_read);
if (checksum != new_checksum) {
return FLASH_PROGRAM_WRITE_VERIFY_ERROR;
}
}
return FLASH_PROGRAM_SUCCESS;
}