BX_CPU_C::read_virtual_byte(unsigned s, bx_address offset, Bit8u *data)
{
bx_address laddr;
bx_segment_reg_t *seg;
seg = &BX_CPU_THIS_PTR sregs[s];
if (seg->cache.valid & SegAccessROK) {
if ((Is64BitMode() && IsCanonical(offset))
|| (offset <= seg->cache.u.segment.limit_scaled)) {
unsigned pl;
accessOK:
laddr = BX_CPU_THIS_PTR get_segment_base(s) + offset;
BX_INSTR_MEM_DATA(BX_CPU_ID, laddr, 1, BX_READ);
pl = (CPL==3);
#if BX_SupportGuest2HostTLB
Bit8u *hostAddr = v2h_read_byte(laddr, pl);
if (hostAddr) {
*data = *hostAddr;
return;
}
#endif
access_linear(laddr, 1, pl, BX_READ, (void *) data);
return;
}
}
read_virtual_checks(seg, offset, 1);
goto accessOK;
}
BX_CPU_C::read_virtual_qword(unsigned s, bx_address offset)
{
bx_address laddr;
bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
Bit64u data;
BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 8, BX_READ);
if (seg->cache.valid & SegAccessROK4G) {
accessOK:
laddr = BX_CPU_THIS_PTR get_laddr(s, offset);
#if BX_SupportGuest2HostTLB
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 7);
bx_address lpf = AlignedAccessLPFOf(laddr, 7);
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, BX_READ);
Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset);
ReadHostQWordFromLittleEndian(hostAddr, data);
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
tlbEntry->ppf | pageOffset, 8, CPL, BX_READ, (Bit8u*) &data);
return data;
}
}
#endif
#if BX_SUPPORT_X86_64
if (! IsCanonical(laddr)) {
BX_ERROR(("read_virtual_qword(): canonical failure"));
exception(int_number(seg), 0, 0);
}
#endif
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
if (BX_CPU_THIS_PTR alignment_check()) {
if (laddr & 7) {
BX_ERROR(("read_virtual_qword(): #AC misaligned access"));
exception(BX_AC_EXCEPTION, 0, 0);
}
}
#endif
access_read_linear(laddr, 8, CPL, BX_READ, (void *) &data);
return data;
}
if (seg->cache.valid & SegAccessROK) {
if (Is64BitMode() || (offset <= (seg->cache.u.segment.limit_scaled-7)))
goto accessOK;
}
read_virtual_checks(seg, offset, 8);
goto accessOK;
}
BX_CPU_C::read_virtual_qword(unsigned s, bx_address offset, Bit64u *data)
{
bx_address laddr;
bx_segment_reg_t *seg;
seg = &BX_CPU_THIS_PTR sregs[s];
if (seg->cache.valid & SegAccessROK) {
if ((Is64BitMode() && IsCanonical(offset))
|| (offset <= (seg->cache.u.segment.limit_scaled-7))) {
unsigned pl;
accessOK:
laddr = BX_CPU_THIS_PTR get_segment_base(s) + offset;
BX_INSTR_MEM_DATA(BX_CPU_ID, laddr, 8, BX_READ);
pl = (CPL==3);
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
if (pl && BX_CPU_THIS_PTR alignment_check) {
if (laddr & 7) {
BX_ERROR(("read_virtual_qword(): misaligned access"));
exception(BX_AC_EXCEPTION, 0, 0);
}
}
#endif
#if BX_SupportGuest2HostTLB
Bit64u *hostAddr = v2h_read_qword(laddr, pl);
if (hostAddr) {
ReadHostQWordFromLittleEndian(hostAddr, *data);
return;
}
#endif
access_linear(laddr, 8, pl, BX_READ, (void *) data);
return;
}
}
read_virtual_checks(seg, offset, 8);
goto accessOK;
}
