STORAGE_CLASS_INLINE void mipi_port_get_state(
const rx_ID_t ID,
const mipi_port_ID_t port_ID,
mipi_port_state_t *state)
{
int i;
assert(ID < N_RX_ID);
assert(port_ID < N_MIPI_PORT_ID);
assert(state != NULL);
state->device_ready = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX);
state->irq_status = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX);
state->irq_enable = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX);
state->timeout_count = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_TIMEOUT_COUNT_REG_IDX);
state->init_count = (uint16_t)receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX);
state->raw16_18 = (uint16_t)receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_RAW16_18_DATAID_REG_IDX);
state->sync_count = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_SYNC_COUNT_REG_IDX);
state->rx_count = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX);
for (i = 0; i < MIPI_4LANE_CFG ; i++) {
state->lane_sync_count[i] = (uint8_t)((state->sync_count)>>(i*8));
state->lane_rx_count[i] = (uint8_t)((state->rx_count)>>(i*8));
}
return;
}
rx_irq_info_t receiver_get_irq_info(
const rx_ID_t ID,
const mipi_port_ID_t port_ID)
{
return receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX);
}
bool is_receiver_port_enabled(
const rx_ID_t ID,
const mipi_port_ID_t port_ID)
{
return (receiver_port_reg_load(ID, port_ID,
_HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX) != 0);
}
/* This is a device function, shouldn't be here */
static void sh_css_rx_set_bits(
const mipi_port_ID_t port,
const unsigned int reg,
const unsigned int lsb,
const unsigned int bits,
const unsigned int val)
{
hrt_data data = receiver_port_reg_load(RX0_ID, port, reg);
/* prevent writing out of range */
hrt_data tmp = val & ((1U << bits) - 1);
/* shift into place */
data |= (tmp << lsb);
receiver_port_reg_store(RX0_ID, port, reg, data);
return;
}
void ia_css_rx_clear_irq_info(unsigned int irq_infos)
{
hrt_data bits = receiver_port_reg_load(RX0_ID,
MIPI_PORT1_ID,
_HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX);
/* MW: Why do we remap the receiver bitmap */
if (irq_infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT;
#if defined(HAS_RX_VERSION_2)
if (irq_infos & IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT;
#endif
if (irq_infos & IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ECC_CORRECTED)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_SOT)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_CRC)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT;
receiver_port_reg_store(RX0_ID,
MIPI_PORT1_ID,
_HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, bits);
return;
}
void
ia_css_rx_get_irq_info(unsigned int *irq_infos)
{
unsigned long infos = 0;
hrt_data bits = receiver_port_reg_load(RX0_ID,
MIPI_PORT1_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX);
assert(irq_infos != NULL);
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT))
infos |= IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN;
#if defined(HAS_RX_VERSION_2)
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT))
infos |= IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT;
#endif
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT))
infos |= IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE;
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT))
infos |= IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE;
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT))
infos |= IA_CSS_RX_IRQ_INFO_ECC_CORRECTED;
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT))
infos |= IA_CSS_RX_IRQ_INFO_ERR_SOT;
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT))
infos |= IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC;
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT))
infos |= IA_CSS_RX_IRQ_INFO_ERR_CONTROL;
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT))
infos |= IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE;
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT))
infos |= IA_CSS_RX_IRQ_INFO_ERR_CRC;
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT))
infos |= IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID;
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT))
infos |= IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC;
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT))
infos |= IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA;
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT))
infos |= IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT;
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT))
infos |= IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC;
if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT))
infos |= IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC;
*irq_infos = infos;
}
void receiver_port_enable(
const rx_ID_t ID,
const mipi_port_ID_t port_ID,
const bool cnd)
{
hrt_data reg = receiver_port_reg_load(ID, port_ID,
_HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX);
if (cnd) {
reg |= 0x01;
} else {
reg &= ~0x01;
}
receiver_port_reg_store(ID, port_ID,
_HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX, reg);
return;
}
void ia_css_isys_rx_enable_all_interrupts(void)
{
hrt_data bits = receiver_port_reg_load(RX0_ID,
MIPI_PORT1_ID,
_HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX);
bits |= (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT) |
#if defined(HAS_RX_VERSION_2)
(1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT) |
#endif
(1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT) |
/*(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT) | */
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT);
/*(1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT); */
receiver_port_reg_store(RX0_ID,
MIPI_PORT1_ID,
_HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, bits);
/*
* The CSI is nested into the Iunit IRQ's
*/
ia_css_irq_enable(IA_CSS_IRQ_INFO_CSS_RECEIVER_ERROR, true);
return;
}
unsigned int sh_css_rx_get_interrupt_reg(void)
{
return receiver_port_reg_load(RX0_ID,
MIPI_PORT1_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX);
}
/* STORAGE_CLASS_INLINE void mipi_port_get_state( */
static void mipi_port_get_state(
const rx_ID_t ID,
const mipi_port_ID_t port_ID,
mipi_port_state_t *state)
{
assert(ID < N_RX_ID);
assert(port_ID < N_MIPI_PORT_ID);
assert(state != NULL);
state->device_ready = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX);
state->irq_status = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX);
state->irq_enable = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX);
state->func_prog = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX);
state->init_count = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX);
state->comp_format = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_COMP_FORMAT_REG_IDX);
state->comp_predict = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_COMP_PREDICT_REG_IDX);
state->fs_to_ls_delay = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX);
state->ls_to_data_delay = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_LS_TO_DATA_DELAY_REG_IDX);
state->data_to_le_delay = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_DATA_TO_LE_DELAY_REG_IDX);
state->le_to_fe_delay = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_LE_TO_FE_DELAY_REG_IDX);
state->fe_to_fs_delay = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_FE_TO_FS_DELAY_REG_IDX);
state->le_to_fs_delay = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_LE_TO_LS_DELAY_REG_IDX);
state->is_two_ppc = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX);
return;
}
unsigned int ia_css_isys_rx_get_interrupt_reg(mipi_port_ID_t port)
{
return receiver_port_reg_load(RX0_ID,
port,
_HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX);
}
