void receiver_set_compression(
const rx_ID_t ID,
const unsigned int cfg_ID,
const mipi_compressor_t comp,
const mipi_predictor_t pred)
{
const mipi_port_ID_t port_ID = (mipi_port_ID_t)cfg_ID;
uint8_t comp_bits, uncomp_bits;
hrt_data reg;
assert(ID < N_RX_ID);
assert(cfg_ID < N_MIPI_COMPRESSOR_CONTEXT);
assert(port_ID < N_MIPI_PORT_ID);
assert(comp < N_MIPI_COMPRESSOR_METHODS);
assert(pred < N_MIPI_PREDICTOR_TYPES);
comp_bits = mipi_compressed_bits[comp];
uncomp_bits = mipi_uncompressed_bits[comp];
assert(comp_bits != 0);
assert(uncomp_bits != 0);
reg = (((hrt_data)uncomp_bits) << 8) | comp_bits;
receiver_port_reg_store(ID,
port_ID, _HRT_CSS_RECEIVER_COMP_FORMAT_REG_IDX, reg);
reg = (hrt_data)pred;
receiver_port_reg_store(ID,
port_ID, _HRT_CSS_RECEIVER_COMP_PREDICT_REG_IDX, reg);
return;
}
void sh_css_rx_disable(void)
{
mipi_port_ID_t port;
for (port = (mipi_port_ID_t)0; port < N_MIPI_PORT_ID; port++) {
receiver_port_reg_store(RX0_ID, port,
_HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX, false);
}
return;
}
void receiver_irq_clear(
const rx_ID_t ID,
const mipi_port_ID_t port_ID,
const rx_irq_info_t irq_info)
{
receiver_port_reg_store(ID,
port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX, irq_info);
return;
}
void receiver_irq_enable(
const rx_ID_t ID,
const mipi_port_ID_t port_ID,
const rx_irq_info_t irq_info)
{
receiver_port_reg_store(ID,
port_ID, _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, irq_info);
return;
}
void receiver_port_enable(
const rx_ID_t ID,
const mipi_port_ID_t port_ID,
const bool cnd)
{
receiver_port_reg_store(ID, port_ID,
_HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX, (hrt_data)cnd);
return;
}
static void sh_css_rx_set_compression(
const mipi_port_ID_t port,
const mipi_predictor_t comp)
{
unsigned int reg = _HRT_CSS_RECEIVER_COMP_PREDICT_REG_IDX;
assert(comp < N_MIPI_PREDICTOR_TYPES);
receiver_port_reg_store(RX0_ID, port, reg, comp);
return;
}
/* This is a device function, shouldn't be here */
static void sh_css_rx_set_bits(
const mipi_port_ID_t port,
const unsigned int reg,
const unsigned int lsb,
const unsigned int bits,
const unsigned int val)
{
hrt_data data = receiver_port_reg_load(RX0_ID, port, reg);
/* prevent writing out of range */
hrt_data tmp = val & ((1U << bits) - 1);
/* shift into place */
data |= (tmp << lsb);
receiver_port_reg_store(RX0_ID, port, reg, data);
return;
}
void ia_css_rx_clear_irq_info(unsigned int irq_infos)
{
hrt_data bits = receiver_port_reg_load(RX0_ID,
MIPI_PORT1_ID,
_HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX);
/* MW: Why do we remap the receiver bitmap */
if (irq_infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT;
#if defined(HAS_RX_VERSION_2)
if (irq_infos & IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT;
#endif
if (irq_infos & IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ECC_CORRECTED)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_SOT)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_CRC)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT;
if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC)
bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT;
receiver_port_reg_store(RX0_ID,
MIPI_PORT1_ID,
_HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, bits);
return;
}
void receiver_port_enable(
const rx_ID_t ID,
const mipi_port_ID_t port_ID,
const bool cnd)
{
hrt_data reg = receiver_port_reg_load(ID, port_ID,
_HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX);
if (cnd) {
reg |= 0x01;
} else {
reg &= ~0x01;
}
receiver_port_reg_store(ID, port_ID,
_HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX, reg);
return;
}
void ia_css_isys_rx_enable_all_interrupts(void)
{
hrt_data bits = receiver_port_reg_load(RX0_ID,
MIPI_PORT1_ID,
_HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX);
bits |= (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT) |
#if defined(HAS_RX_VERSION_2)
(1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT) |
#endif
(1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT) |
/*(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT) | */
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT) |
(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT);
/*(1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT); */
receiver_port_reg_store(RX0_ID,
MIPI_PORT1_ID,
_HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, bits);
/*
* The CSI is nested into the Iunit IRQ's
*/
ia_css_irq_enable(IA_CSS_IRQ_INFO_CSS_RECEIVER_ERROR, true);
return;
}
void sh_css_rx_configure(
const rx_cfg_t *config,
const enum ia_css_input_mode input_mode)
{
#if defined(HAS_RX_VERSION_2)
bool port_enabled[N_MIPI_PORT_ID];
bool any_port_enabled = false;
mipi_port_ID_t port;
assert(config != NULL);
for (port = (mipi_port_ID_t)0; port < N_MIPI_PORT_ID; port++) {
if (is_receiver_port_enabled(RX0_ID, port))
any_port_enabled = true;
}
/* AM: Check whether this is a problem with multiple streams. MS: This is the case.*/
/* Must turn off all ports because of the 2ppc setting */
#ifdef THIS_CODE_IS_NO_LONGER_NEEDED_FOR_DUAL_STREAM
for (port = (mipi_port_ID_t)0; port < N_MIPI_PORT_ID; port++) {
port_enabled[port] = is_receiver_port_enabled(RX0_ID, port);
receiver_port_enable(RX0_ID, port, false);
}
#else
port = config->port;
receiver_port_enable(RX0_ID, port, false);
#endif
port = config->port;
/* AM: Check whether this is a problem with multiple streams. */
if (MIPI_PORT_LANES[config->mode][port] != MIPI_0LANE_CFG) {
receiver_port_reg_store(RX0_ID, port,
_HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX,
config->timeout);
receiver_port_reg_store(RX0_ID, port,
_HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX,
config->initcount);
receiver_port_reg_store(RX0_ID, port,
_HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX,
config->synccount);
receiver_port_reg_store(RX0_ID, port,
_HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX,
config->rxcount);
port_enabled[port] = true;
if (input_mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR) {
/* MW: A bit of a hack, straight wiring of the capture units,assuming they are linearly enumerated. */
input_system_sub_system_reg_store(INPUT_SYSTEM0_ID,
GPREGS_UNIT0_ID, HIVE_ISYS_GPREG_MULTICAST_A_IDX +
(unsigned int)port, INPUT_SYSTEM_CSI_BACKEND);
/* MW: Like the integration test example we overwite, the GPREG_MUX register */
input_system_sub_system_reg_store(INPUT_SYSTEM0_ID,
GPREGS_UNIT0_ID, HIVE_ISYS_GPREG_MUX_IDX,
(input_system_multiplex_t)port);
} else {
/*
* AM: A bit of a hack, wiring the input system.
*/
input_system_sub_system_reg_store(INPUT_SYSTEM0_ID,
GPREGS_UNIT0_ID, HIVE_ISYS_GPREG_MULTICAST_A_IDX +
(unsigned int)port, INPUT_SYSTEM_INPUT_BUFFER);
input_system_sub_system_reg_store(INPUT_SYSTEM0_ID,
GPREGS_UNIT0_ID, HIVE_ISYS_GPREG_MUX_IDX,
INPUT_SYSTEM_ACQUISITION_UNIT);
}
}
/*
* The 2ppc is shared for all ports, so we cannot disable->configure->enable individual ports
*/
/* AM: Check whether this is a problem with multiple streams. */
/* MS: 2ppc should be a property per binary and should be enabled/disabled per binary.
Currently it is implemented as a system wide setting due to effort and risks. */
if (!any_port_enabled) {
receiver_reg_store(RX0_ID,
_HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX, config->is_two_ppc);
receiver_reg_store(RX0_ID,
_HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX, config->is_two_ppc);
}
#ifdef THIS_CODE_IS_NO_LONGER_NEEDED_FOR_DUAL_STREAM
/* enable the selected port(s) */
for (port = (mipi_port_ID_t)0; port < N_MIPI_PORT_ID; port++) {
receiver_port_enable(RX0_ID, port, port_enabled[port]);
}
#else
receiver_port_enable(RX0_ID, port, true);
#endif
// TODO: JB: need to add the beneath used define to mizuchi
// sh_css_sw_hive_isp_css_2400A0_system_20121224_0125\css\hrt\input_system_defs.h
// #define INPUT_SYSTEM_CSI_RECEIVER_SELECT_BACKENG 0X207
// TODO: need better name for define
//input_system_reg_store(INPUT_SYSTEM0_ID, INPUT_SYSTEM_CSI_RECEIVER_SELECT_BACKENG, 1);
input_system_reg_store(INPUT_SYSTEM0_ID, 0x207, 1);
#elif defined(HAS_RX_VERSION_1)
mipi_port_ID_t port = config->port;
(void) input_mode; //AM: just to satisfy the compiler.
/* turn off all ports just in case */
sh_css_rx_disable();
/* All settings are per port */
sh_css_rx_set_timeout(port, config->timeout);
/* configure the selected port */
sh_css_rx_set_num_lanes(port, config->num_lanes);
sh_css_rx_set_compression(port, config->comp);
sh_css_rx_set_uncomp_size(port, config->uncomp_bpp);
sh_css_rx_set_comp_size(port, config->comp_bpp);
receiver_port_reg_store(RX0_ID, port,
_HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX, config->is_two_ppc);
/* enable the selected port */
receiver_port_reg_store(RX0_ID, port,
_HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX, true);
#else
#error "sh_css_rx.c: RX version must be one of {RX_VERSION_1, RX_VERSION_2}"
#endif
return;
}
