Пример #1
0
static void bit_clear_pwm0(unsigned long addr,unsigned gpio)
{
  void * virt_addr;
  unsigned long mask;

  virt_addr = map_base_pwm0 + ((addr+(gpio/32)*4) & MAP_MASK);
  mask      = 1 << (gpio%32);
  
  reg_val(virt_addr) = reg_val(virt_addr) & ~mask;
}
Пример #2
0
static long int get_reg_pwm0(unsigned long addr)
{
  void * virt_addr;

  virt_addr = map_base_pwm0 + (addr & MAP_MASK);
 
  return reg_val(virt_addr);
}
Пример #3
0
static void reg_set_pwm0(unsigned long addr,unsigned long value)
{
  void * virt_addr;

 virt_addr = map_base_pwm0 + (addr & MAP_MASK);
 
  reg_val(virt_addr) = value;
}
Пример #4
0
static int bit_test_pwm0(unsigned long addr,unsigned gpio)
{
  void * virt_addr;
  unsigned long mask;

  virt_addr = map_base_pwm0 + ((addr+(gpio/32)*4) & MAP_MASK);
  mask      = 1 << (gpio%32);
  
  if(reg_val(virt_addr) & mask)
    return 1;
  else
    return 0;
}
Пример #5
0
static int l_rnn_etype(lua_State *L, struct rnn *rnn,
		struct rnndelem *elem, uint64_t offset)
{
	int ret;
	DBG("elem=%p (%d), offset=%lu", elem, elem->type, offset);
	switch (elem->type) {
	case RNN_ETYPE_REG:
		/* if a register has no bitfields, just return
		 * the raw value:
		 */
		ret = pushdecval(L, rnn, reg_val(offset), &elem->typeinfo);
		if (ret)
			return ret;
		return l_rnn_etype_reg(L, rnn, elem, offset);
	case RNN_ETYPE_ARRAY:
		return l_rnn_etype_array(L, rnn, elem, offset);
	default:
		/* hmm.. */
		printf("unhandled type: %d\n", elem->type);
		return 0;
	}
}
Пример #6
0
static int l_rnn_reg_meta_index(lua_State *L)
{
	struct rnndoff *rnndoff = lua_touserdata(L, 1);
	const char *name = lua_tostring(L, 2);
	struct rnndelem *elem = rnndoff->elem;
	struct rnntypeinfo *info = &elem->typeinfo;
	struct rnnbitfield **bitfields;
	int bitfieldsnum;
	int i;

	switch (info->type) {
	case RNN_TTYPE_BITSET:
		bitfields = info->ebitset->bitfields;
		bitfieldsnum = info->ebitset->bitfieldsnum;
		break;
	case RNN_TTYPE_INLINE_BITSET:
		bitfields = info->bitfields;
		bitfieldsnum = info->bitfieldsnum;
		break;
	default:
		printf("invalid register type: %d\n", info->type);
		return 0;
	}

	for (i = 0; i < bitfieldsnum; i++) {
		struct rnnbitfield *bf = bitfields[i];
		if (!strcmp(name, bf->name)) {
			uint32_t regval = (reg_val(rnndoff->offset) & bf->mask) >> bf->low;

			DBG("name=%s, info=%p, subelemsnum=%d, type=%d, regval=%x",
					name, info, rnndoff->elem->subelemsnum,
					bf->typeinfo.type, regval);

			return pushdecval(L, rnndoff->rnn, regval, &bf->typeinfo);
		}
	}
Пример #7
0
#define asiu_gate_val(o, es) { .offset = o, .en_shift = es }

static void __init cygnus_armpll_init(struct device_node *node)
{
	iproc_armpll_setup(node);
}
CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);

static const struct iproc_pll_ctrl genpll = {
	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
		IPROC_CLK_PLL_NEEDS_SW_CFG,
	.aon = aon_val(0x0, 2, 1, 0),
	.reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
	.sw_ctrl = sw_ctrl_val(0x10, 31),
	.ndiv_int = reg_val(0x10, 20, 10),
	.ndiv_frac = reg_val(0x10, 0, 20),
	.pdiv = reg_val(0x14, 0, 4),
	.vco_ctrl = vco_ctrl_val(0x18, 0x1c),
	.status = reg_val(0x28, 12, 1),
};

static const struct iproc_clk_ctrl genpll_clk[] = {
	[BCM_CYGNUS_GENPLL_AXI21_CLK] = {
		.channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
		.flags = IPROC_CLK_AON,
		.enable = enable_val(0x4, 6, 0, 12),
		.mdiv = reg_val(0x20, 0, 8),
	},
	[BCM_CYGNUS_GENPLL_250MHZ_CLK] = {
		.channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,