C++ (Cpp) registerOutputPort примеры использования

Пример #1

Файл: TcpSocketRxComponent.cpp Проект: mcgettrs/iris_modules

void TcpSocketRxComponent::registerPorts()
{
  //Register all ports
  //This component supports all data types
  vector<int> validTypes = convertToTypeIdVector<IrisDataTypes>();

  //format:        (name, vector of valid types)
  registerOutputPort("output1", validTypes);
}

Пример #2

Файл: SpectrogramComponent.cpp Проект: antiface/BasicCR

void SpectrogramComponent::registerPorts()
{
  registerInputPort("input1", TypeInfo< complex<float> >::identifier);
  if(!isSink_x)
  {
    std::vector<int> types;
    types.push_back(TypeInfo< float >::identifier);
    types.push_back(TypeInfo< complex<float> >::identifier);
    registerOutputPort("output1", types);
  }
}

Пример #3

Файл: PfbSynthesizerComponent.cpp Проект: andrepuschmann/iris_modules

void PfbSynthesizerComponent::registerPorts()
{
  for(int i=0; i<nChans_x; i++)
  {
    stringstream ss;
    ss << "input";
    ss << i;
    registerInputPort(ss.str(), TypeInfo< complex<float> >::identifier);
  }

  registerOutputPort("output1", TypeInfo< complex<float> >::identifier);
}

Пример #4

Файл: MatlabTemplateComponent.cpp Проект: mcgettrs/iris_modules

void MatlabTemplateComponent::registerPorts()
{
  //This component accepts all the Iris data types
  vector<int> validTypes = convertToTypeIdVector<IrisDataTypes>();

  //format:        (name, vector of valid types)
  registerInputPort("input1", validTypes);

  if(hasOutput_x || passThrough_x)
  {
    registerOutputPort("output1", validTypes);
  }
}

Пример #5

Файл: UdpSocketRxComponent.cpp Проект: mcgettrs/iris_modules

void UdpSocketRxComponent::registerPorts()
{
  //Register all ports
  vector<int> validTypes; //This component supports all data types
  validTypes.push_back( int(TypeInfo< uint8_t >::identifier) );
  validTypes.push_back( int(TypeInfo< uint16_t >::identifier) );
  validTypes.push_back( int(TypeInfo< uint32_t >::identifier) );
  validTypes.push_back( int(TypeInfo< uint64_t >::identifier) );
  validTypes.push_back( int(TypeInfo< int8_t >::identifier) );
  validTypes.push_back( int(TypeInfo< int16_t >::identifier) );
  validTypes.push_back( int(TypeInfo< int32_t >::identifier) );
  validTypes.push_back( int(TypeInfo< int64_t >::identifier) );
  validTypes.push_back( int(TypeInfo< float >::identifier) );
  validTypes.push_back( int(TypeInfo< double >::identifier) );
  validTypes.push_back( int(TypeInfo< long double >::identifier) );
  validTypes.push_back( int(TypeInfo< complex<float> >::identifier) );
  validTypes.push_back( int(TypeInfo< complex<double> >::identifier) );
  validTypes.push_back( int(TypeInfo< complex<long double> >::identifier) );

  //format:        (name, vector of valid types)
  registerOutputPort("output1", validTypes);
}

Пример #6

Файл: FileRawReaderComponent.cpp Проект: mcgettrs/iris_modules

void FileRawReaderComponent::registerPorts()
{
  //Register all ports
  vector<int> validTypes;
  validTypes.push_back( int(TypeInfo< uint8_t >::identifier) );
  validTypes.push_back( int(TypeInfo< uint16_t >::identifier) );
  validTypes.push_back( int(TypeInfo< uint32_t >::identifier) );
  validTypes.push_back( int(TypeInfo< uint64_t >::identifier) );
  validTypes.push_back( int(TypeInfo< int8_t >::identifier) );
  validTypes.push_back( int(TypeInfo< int16_t >::identifier) );
  validTypes.push_back( int(TypeInfo< int32_t >::identifier) );
  validTypes.push_back( int(TypeInfo< int64_t >::identifier) );
  validTypes.push_back( int(TypeInfo< float >::identifier) );
  validTypes.push_back( int(TypeInfo< double >::identifier) );
  validTypes.push_back( int(TypeInfo< long double >::identifier) );
  validTypes.push_back( int(TypeInfo< complex<float> >::identifier) );
  validTypes.push_back( int(TypeInfo< complex<double> >::identifier) );
  validTypes.push_back( int(TypeInfo< complex<long double> >::identifier) );

  //format:        (name, vector of valid types)
  registerOutputPort("output1", validTypes);
}

Пример #7

Файл: PeriodogramComponent.cpp Проект: jvandebelt/iris_modules

void PeriodogramComponent::registerPorts()
{
  registerInputPort("input1", TypeInfo< complex<float> >::identifier);
  registerOutputPort("output1", TypeInfo< float >::identifier);
}

Пример #8

Файл: ExampleComponent.cpp Проект: mcgettrs/iris_modules

void ExampleComponent::registerPorts()
{
  registerInputPort("input1", TypeInfo< uint32_t >::identifier);
  registerOutputPort("output1", TypeInfo< uint32_t >::identifier);
}

Пример #9

Файл: Dvbt1PuncturerComponent.cpp Проект: wishful-project/examples

/// Register the puncturer ports with the IRIS system
///
/// This component has one input that accepts bits (one bit per byte) and one
/// output that provides punctured bits (one bit per byte).
void Dvbt1PuncturerComponent::registerPorts()
{
  registerInputPort("input1", TypeInfo< uint8_t >::identifier);
  registerOutputPort("output1", TypeInfo< uint8_t >::identifier);
}

Пример #10

Файл: LiquidOfdmModComponent.cpp Проект: andrepuschmann/iris_modules

void LiquidOfdmModComponent::registerPorts()
{
    registerInputPort("input1", TypeInfo< uint8_t >::identifier);
    registerOutputPort("output1", TypeInfo< complex<float> >::identifier);
}

Пример #11

Файл: Dvbt1InterpolatorComponent.cpp Проект: wishful-project/examples

/// Register the mapper ports with the IRIS system
///
/// This component has one input that accept complex float values and one
/// output that provides complex float values.
void Dvbt1InterpolatorComponent::registerPorts()
{
  registerInputPort("input1", TypeInfo< Cplx >::identifier);
  registerOutputPort("output1", TypeInfo< Cplx >::identifier);
}

Пример #12

Файл: SignalScalerComponent.cpp Проект: mcgettrs/iris_modules

void SignalScalerComponent::registerPorts()
{
  registerInputPort("input1", TypeInfo< complex<float> >::identifier);
  registerOutputPort("output1", TypeInfo< complex<float> >::identifier);
}

Пример #13

Файл: Serial2ParaComponent.cpp Проект: jvandebelt/iris_modules

void Serial2ParaComponent::registerPorts()
{
  registerInputPort("input1", TypeInfo< float >::identifier);
  registerOutputPort("output1", TypeInfo< float >::identifier);
}