JSValue CallFrame::uncheckedActivation() const { CodeBlock* codeBlock = this->codeBlock(); RELEASE_ASSERT(codeBlock->needsActivation()); VirtualRegister activationRegister = codeBlock->activationRegister(); return registers()[activationRegister.offset()].jsValue(); }
void CallFrame::setActivation(JSLexicalEnvironment* lexicalEnvironment) { CodeBlock* codeBlock = this->codeBlock(); RELEASE_ASSERT(codeBlock->needsActivation()); VirtualRegister activationRegister = codeBlock->activationRegister(); registers()[activationRegister.offset()] = lexicalEnvironment; }
JSLexicalEnvironment* CallFrame::lexicalEnvironment() const { CodeBlock* codeBlock = this->codeBlock(); RELEASE_ASSERT(codeBlock->needsActivation()); VirtualRegister activationRegister = codeBlock->activationRegister(); return registers()[activationRegister.offset()].Register::lexicalEnvironment(); }
SharedShadowNode UITemplateProcessor::buildShadowTree( const std::string &jsonStr, Tag rootTag, const folly::dynamic ¶ms, const ComponentDescriptorRegistry &componentDescriptorRegistry, const NativeModuleRegistry &nativeModuleRegistry, const std::shared_ptr<const ReactNativeConfig> reactNativeConfig) { LOG(INFO) << "(strt) UITemplateProcessor inject hardcoded 'server rendered' view tree"; std::string content = jsonStr; for (const auto ¶m : params.items()) { const auto &key = param.first.asString(); size_t start_pos = content.find(key); if (start_pos != std::string::npos) { content.replace(start_pos, key.length(), param.second.asString()); } } auto parsed = folly::parseJson(content); auto commands = parsed["commands"]; std::vector<SharedShadowNode> nodes(commands.size() * 2); std::vector<folly::dynamic> registers(32); for (const auto &command : commands) { try { if (DEBUG_FLY) { LOG(INFO) << "try to run command " << folly::toJson(command); } auto ret = runCommand( command, rootTag, nodes, registers, componentDescriptorRegistry, nativeModuleRegistry, reactNativeConfig); if (ret != nullptr) { return ret; } } catch (const std::exception &e) { LOG(ERROR) << " >>> Exception <<< running previous command '" << folly::toJson(command) << "': '" << e.what() << "'"; } } LOG(ERROR) << "react ui template missing returnRoot command :("; throw std::runtime_error( "Missing returnRoot command in template content:\n" + content); return SharedShadowNode{}; }
QModbusResponse QModbusServerPrivate::processWriteMultipleRegistersRequest( const QModbusRequest &request) { CHECK_SIZE_LESS_THAN(request); quint16 address, numberOfRegisters; quint8 byteCount; request.decodeData(&address, &numberOfRegisters, &byteCount); // byte count does not match number of data bytes following or register count if ((byteCount != (request.dataSize() - 5 )) || (byteCount != (numberOfRegisters * 2))) { return QModbusExceptionResponse(request.functionCode(), QModbusExceptionResponse::IllegalDataValue); } if ((numberOfRegisters < 0x0001) || (numberOfRegisters > 0x007B)) { return QModbusExceptionResponse(request.functionCode(), QModbusExceptionResponse::IllegalDataValue); } // Get the requested range out of the registers. QModbusDataUnit registers(QModbusDataUnit::HoldingRegisters, address, numberOfRegisters); if (!q_func()->data(®isters)) { return QModbusExceptionResponse(request.functionCode(), QModbusExceptionResponse::IllegalDataAddress); } const QByteArray pduData = request.data().remove(0,5); QDataStream stream(pduData); QVector<quint16> values; quint16 tmp; for (int i = 0; i < numberOfRegisters; i++) { stream >> tmp; values.append(tmp); } registers.setValues(values); if (!q_func()->setData(registers)) { return QModbusExceptionResponse(request.functionCode(), QModbusExceptionResponse::ServerDeviceFailure); } return QModbusResponse(request.functionCode(), address, numberOfRegisters); }
void SAM(C64 *the_c64) { bool done = false; char c; TheCPU = the_c64->TheCPU; TheCPU1541 = the_c64->TheCPU1541; TheVIC = the_c64->TheVIC; TheSID = the_c64->TheSID; TheCIA1 = the_c64->TheCIA1; TheCIA2 = the_c64->TheCIA2; // Get CPU registers and current memory configuration TheCPU->GetState(&R64); TheCPU->ExtConfig = (~R64.ddr | R64.pr) & 7; TheCPU1541->GetState(&R1541); #ifdef __riscos__ Wimp_CommandWindow((int)"SAM"); #endif #ifdef AMIGA if (!(fin = fout = ferr = fopen("CON:0/0/640/480/SAM", "w+"))) return; #else fin = stdin; fout = stdout; ferr = stdout; #endif access_1541 = false; address = R64.pc; fprintf(ferr, "\n *** SAM - Simple Assembler and Monitor ***\n *** Press 'h' for help ***\n\n"); init_abort(); display_registers(); while (!done) { if (access_1541) fprintf(ferr, "1541> "); else fprintf(ferr, "C64> "); fflush(ferr); read_line(); while ((c = get_char()) == ' ') ; switch (c) { case 'a': // Assemble get_token(); assemble(); break; case 'b': // Binary dump get_token(); binary_dump(); break; case 'c': // Compare get_token(); compare(); break; case 'd': // Disassemble get_token(); disassemble(); break; case 'e': // Interrupt vectors int_vectors(); break; case 'f': // Fill get_token(); fill(); break; case 'h': // Help help(); break; case 'i': // ASCII dump get_token(); ascii_dump(); break; case 'k': // Memory configuration get_token(); mem_config(); break; case 'l': // Load data get_token(); load_data(); break; case 'm': // Memory dump get_token(); memory_dump(); break; case 'n': // Screen code dump get_token(); screen_dump(); break; case 'o': // Redirect output get_token(); redir_output(); break; case 'p': // Sprite dump get_token(); sprite_dump(); break; case 'r': // Registers get_reg_token(); registers(); break; case 's': // Save data get_token(); save_data(); break; case 't': // Transfer get_token(); transfer(); break; case 'v': // View machine state view_state(); break; case 'x': // Exit done = true; break; case ':': // Change memory get_token(); modify(); break; case '1': // Switch to 1541 mode access_1541 = true; break; case '6': // Switch to C64 mode access_1541 = false; break; case '?': // Compute expression get_token(); print_expr(); break; case '\n': // Blank line break; default: // Unknown command error("Unknown command"); break; } } exit_abort(); #ifdef AMIGA fclose(fin); #endif if (fout != ferr) fclose(fout); #ifdef __riscos__ Wimp_CommandWindow(-1); #endif // Set CPU registers TheCPU->SetState(&R64); TheCPU1541->SetState(&R1541); }
bool ErrorReport::GetMiscCrashInfo() { // Get crash time m_CrashDateTime = QDateTime::currentDateTime(); m_ProcessArchitecture = ARX_ARCH_NAME; m_OSName = QString::fromUtf8(platform::getOSName().c_str()); m_OSArchitecture = QString::fromUtf8(platform::getOSArchitecture().c_str()); m_OSDistribution = QString::fromUtf8(platform::getOSDistribution().c_str()); #if ARX_PLATFORM == ARX_PLATFORM_WIN32 // Open parent process handle HANDLE hProcess = OpenProcess(PROCESS_ALL_ACCESS, FALSE, m_pCrashInfo->processId); if(hProcess != NULL) { // Get memory usage info PROCESS_MEMORY_COUNTERS meminfo; BOOL bGetMemInfo = GetProcessMemoryInfo(hProcess, &meminfo, sizeof(PROCESS_MEMORY_COUNTERS)); if(bGetMemInfo) m_ProcessMemoryUsage = meminfo.WorkingSetSize; // Determine the period of time the process is working. FILETIME CreationTime, ExitTime, KernelTime, UserTime; BOOL bGetTimes = GetProcessTimes(hProcess, &CreationTime, &ExitTime, &KernelTime, &UserTime); if(bGetTimes) { SYSTEMTIME AppStartTime; FileTimeToSystemTime(&CreationTime, &AppStartTime); SYSTEMTIME CurTime; GetSystemTime(&CurTime); ULONG64 uCurTime = ConvertSystemTimeToULONG64(CurTime); ULONG64 uStartTime = ConvertSystemTimeToULONG64(AppStartTime); // Check that the application works for at least one minute before crash. // This might help to avoid cyclic error report generation when the applciation // crashes on startup. m_RunningTimeSec = (double)(uCurTime-uStartTime)*10E-08; } } else { m_DetailedError = QString("Unable to obtain an handle to the crashed process (Error %1).").arg(QString::number(GetLastError())); return false; } if(m_pCrashInfo->exceptionCode != 0) { QString exceptionStr = GetExceptionString(m_pCrashInfo->exceptionCode).c_str(); if(!exceptionStr.isEmpty()) { m_ReportDescription += "\nException code:\n "; m_ReportDescription += exceptionStr; m_ReportDescription += "\n"; } } std::string callStack, callstackTop; u32 callstackCrc; bool bCallstack = GetCallStackInfo(hProcess, m_pCrashInfo->threadHandle, &m_pCrashInfo->contextRecord, callStack, callstackTop, callstackCrc); if(!bCallstack) { m_DetailedError = "A failure occured when obtaining information regarding the callstack."; return false; } m_ReportUniqueID = QString("[%1]").arg(QString::number(callstackCrc, 16).toUpper()); m_ReportDescription = m_pCrashInfo->detailedCrashInfo; m_ReportDescription += "\nCallstack:\n"; m_ReportDescription += callStack.c_str(); m_ReportTitle = QString("%1 %2").arg(m_ReportUniqueID, callstackTop.c_str()); QString registers(GetRegisters(&m_pCrashInfo->contextRecord).c_str()); if(!registers.isEmpty()) { m_ReportDescription += "\nRegisters:\n"; m_ReportDescription += registers; } CloseHandle(hProcess); m_ReportDescriptionText = m_ReportDescription; #else // ARX_PLATFORM != ARX_PLATFORM_WIN32 getResourceUsage(m_pCrashInfo->processId, m_ProcessMemoryUsage, m_RunningTimeSec); #endif return true; }
Register* CallFrame::frameExtentInternal() { CodeBlock* codeBlock = this->codeBlock(); ASSERT(codeBlock); return registers() + codeBlock->m_numCalleeRegisters; }
Register* CallFrame::topOfFrameInternal() { CodeBlock* codeBlock = this->codeBlock(); ASSERT(codeBlock); return registers() + codeBlock->stackPointerOffset(); }
/* * machine.cpp * * Baker, Ballard, Jager-Kujawa * CSC 341 * Spring 2016 */ #include "machine.hpp" int *sysclock; // Keep track of absolute time int timer_interrupt; // Send interrupt every QUANTUM ticks // Initialize machine registers registers machine = registers(0, 0, 0, 0, 0, 0, 0); // Declare main memory unsigned short int main_memory[256]; // Memory Management Unit // Takes a logical address and converts it to a physical address // by looking up frame numbers in the table store in PTBR // Throws out_of_range exception if PTBR is null unsigned short int MMU(unsigned short int logicalAddress) { if (!machine.PTBR) { // If PTBR pointer is null, throw an exception throw std::out_of_range("Page table base register is not initialized!"); } unsigned short int page = (logicalAddress&252)>>2; // Returns 0-63 unsigned short int offset = logicalAddress & 3; // Returns 0-3
int main() { show(); flags(); registers(); }
int sc_main(int argc, char* argv[]) { sc_report_handler:: set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING); char stbuf[256]; // SIGNALS // Data signals sc_signal< sc_bv<DWORD> > bus_mux1; sc_signal< sc_bv<DWORD> > bus_mux2; sc_signal< sc_bv<DWORD> > bus_mux3; sc_signal< sc_bv<AWORDREG> > bus_mux4; sc_signal< sc_bv<6> > bus_decoder_instr_31_26; sc_signal< sc_bv<AWORDREG> > bus_decoder_instr_25_21; sc_signal< sc_bv<AWORDREG> > bus_decoder_instr_20_16; sc_signal< sc_bv<AWORDREG> > bus_decoder_instr_15_11; sc_signal< sc_bv<SIGNEXTENDBIT> > bus_decoder_instr_15_0; sc_signal< sc_bv<6> > bus_decoder_instr_5_0; sc_signal< sc_bv<DWORD> > bus_pc; sc_signal< sc_bv<DWORD> > bus_add1; sc_signal< sc_bv<DWORD> > bus_add2; sc_signal< sc_bv<DWORD> > bus_shiftleft; sc_signal< sc_bv<DWORD> > bus_signextend; sc_signal< sc_bv<DWORD> > bus_imem_1; sc_signal< sc_bv<DWORD> > bus_dmem_1; sc_signal< sc_bv<DWORD> > bus_alu_result; sc_signal< sc_bv<1> > bus_alu_zero; sc_signal< sc_bv<DWORD> > bus_registers_1; sc_signal< sc_bv<DWORD> > bus_registers_2; // Control signals sc_signal< sc_bv<1> > bus_ctrl_regdst; sc_signal< sc_bv<1> > bus_ctrl_branch; sc_signal< sc_bv<1> > bus_ctrl_memread; sc_signal< sc_bv<1> > bus_ctrl_memtoreg; sc_signal< sc_bv<2> > bus_ctrl_aluop; sc_signal< sc_bv<1> > bus_ctrl_memwrite; sc_signal< sc_bv<1> > bus_ctrl_alusrc; sc_signal< sc_bv<1> > bus_ctrl_regwrite; sc_signal< sc_bv<DWORD> > bus_ctrl_c4; sc_signal< sc_bv<3> > bus_aluctrl; sc_signal< sc_bv<1> > bus_and1; // MODULES REGISTER pc("pc"); ADD add1("add1"); ADD add2("add2"); AND and1("and1"); ROM imem("instruction_memory"); // Instruction memory RAM dmem("data_memory"); // Data memory REGFILE registers("registers"); // Registerfile ALU alu("alu"); ALUCTRL aluctrl("aluctrl"); SIGNEXTEND signextend("signextend"); SHIFTLEFT shiftleft("shiftleft"); CTRL ctrl("ctrl"); DECODER decoder("decoder"); MUX mux1("mux1"); MUX mux2("mux2"); MUX mux3("mux3"); MUX2_AWORDREG mux4("mux4"); sc_clock clk("clock", 20); // Clock // CONNECTIONS // Program counter pc.in(bus_mux1); pc.out(bus_pc); pc.w(clk); pc.clk(clk); // Add 1 (PC + 4) add1.a(bus_pc); add1.b(bus_ctrl_c4); add1.r(bus_add1); // Add 2 (add1 + shiftleft) add2.a(bus_add1); add2.b(bus_shiftleft); add2.r(bus_add2); // Mux 1 (add1 or add2) mux1.in0(bus_add1); mux1.in1(bus_add2); mux1.sel(bus_and1); mux1.out(bus_mux1); // Shift left 2 shiftleft.in(bus_signextend); shiftleft.out(bus_shiftleft); // Sign extend signextend.in(bus_decoder_instr_15_0); signextend.out(bus_signextend); // Decoder (Select correct part of instruction for registerfile) decoder.instr(bus_imem_1); decoder.instr_31_26(bus_decoder_instr_31_26); decoder.instr_25_21(bus_decoder_instr_25_21); decoder.instr_20_16(bus_decoder_instr_20_16); decoder.instr_15_11(bus_decoder_instr_15_11); decoder.instr_15_0(bus_decoder_instr_15_0); decoder.instr_5_0(bus_decoder_instr_5_0); // Mux 4 (Select address for write to registerfile) mux4.in0(bus_decoder_instr_20_16); mux4.in1(bus_decoder_instr_15_11); mux4.sel(bus_ctrl_regdst); mux4.out(bus_mux4); // ALU alu.a(bus_registers_1); alu.b(bus_mux2); alu.r(bus_alu_result); alu.z(bus_alu_zero); alu.ctrl(bus_aluctrl); // Mux 2 (Registerfile or signextend) mux2.in0(bus_registers_2); mux2.in1(bus_signextend); mux2.sel(bus_ctrl_alusrc); mux2.out(bus_mux2); // ALU ctrl aluctrl.ALUop(bus_ctrl_aluop); aluctrl.functionCode(bus_decoder_instr_5_0); aluctrl.ALUctrl(bus_aluctrl); // Mux 3 (ALU result or memory result to register) mux3.in0(bus_alu_result); mux3.in1(bus_dmem_1); mux3.sel(bus_ctrl_memtoreg); mux3.out(bus_mux3); // AND and1.a(bus_alu_zero); and1.b(bus_ctrl_branch); and1.r(bus_and1); // Registerfile registers.r_addr_reg1(bus_decoder_instr_25_21); registers.r_addr_reg2(bus_decoder_instr_20_16); registers.w_addr_reg(bus_mux4); registers.r_data_reg1(bus_registers_1); registers.r_data_reg2(bus_registers_2); registers.w_data_reg(bus_mux3); registers.w(bus_ctrl_regwrite); registers.clk(clk); // Data memory dmem.a_read(bus_alu_result); dmem.d_read(bus_dmem_1); dmem.r(bus_ctrl_memread); dmem.a_write(bus_alu_result); dmem.d_write(bus_registers_2); dmem.w(bus_ctrl_memwrite); dmem.clk(clk); // Instruction Memory imem.a_read(bus_pc); imem.d_read(bus_imem_1); imem.clk(clk); // Controller ctrl.Opcode(bus_decoder_instr_31_26); ctrl.RegDst(bus_ctrl_regdst); ctrl.Branch(bus_ctrl_branch); ctrl.MemRead(bus_ctrl_memread); ctrl.MemtoReg(bus_ctrl_memtoreg); ctrl.ALUop(bus_ctrl_aluop); ctrl.MemWrite(bus_ctrl_memwrite); ctrl.ALUSrc(bus_ctrl_alusrc); ctrl.RegWrite(bus_ctrl_regwrite); ctrl.c4(bus_ctrl_c4); // INITIALIZATION imem.rom_init("mips.rom"); dmem.ram_init("mips.ram"); // TRACING sc_trace_file* tf; tf = sc_create_vcd_trace_file("mips"); // Signals sc_trace(tf, clk, "clock"); sc_trace(tf, bus_mux1, "bus_mux1"); sc_trace(tf, bus_mux2, "bus_mux2"); sc_trace(tf, bus_mux3, "bus_mux3"); sc_trace(tf, bus_mux4, "bus_mux4"); sc_trace(tf, bus_pc, "bus_pc"); sc_trace(tf, bus_add1, "bus_add1"); sc_trace(tf, bus_add2, "bus_add2"); sc_trace(tf, bus_shiftleft, "bus_shiftleft"); sc_trace(tf, bus_signextend, "bus_signextend"); sc_trace(tf, bus_imem_1, "bus_imem_1"); sc_trace(tf, bus_dmem_1, "bus_dmem_1"); sc_trace(tf, bus_alu_result, "bus_alu_result"); sc_trace(tf, bus_alu_zero, "bus_alu_zero"); sc_trace(tf, bus_registers_1, "bus_registers_1"); sc_trace(tf, bus_registers_2, "bus_registers_2"); sc_trace(tf, bus_ctrl_regdst, "bus_ctrl_regdst"); sc_trace(tf, bus_ctrl_branch, "bus_ctrl_branch"); sc_trace(tf, bus_ctrl_memread, "bus_ctrl_memread"); sc_trace(tf, bus_ctrl_memtoreg, "bus_ctrl_memtoreg"); sc_trace(tf, bus_ctrl_aluop, "bus_ctrl_aluop"); sc_trace(tf, bus_ctrl_memwrite, "bus_ctrl_memwrite"); sc_trace(tf, bus_ctrl_alusrc, "bus_ctrl_alusrc"); sc_trace(tf, bus_ctrl_regwrite, "bus_ctrl_regwrite"); sc_trace(tf, bus_ctrl_c4, "bus_ctrl_c4"); sc_trace(tf, bus_aluctrl, "bus_aluctrl"); sc_trace(tf, bus_and1, "bus_and1"); sc_trace(tf, bus_decoder_instr_31_26, "bus_decoder_instr_31_26"); sc_trace(tf, bus_decoder_instr_25_21, "bus_decoder_instr_25_21"); sc_trace(tf, bus_decoder_instr_20_16, "bus_decoder_instr_20_16"); sc_trace(tf, bus_decoder_instr_15_11, "bus_decoder_instr_15_11"); sc_trace(tf, bus_decoder_instr_15_0, "bus_decoder_instr_15_0"); sc_trace(tf, bus_decoder_instr_5_0, "bus_decoder_instr_5_0"); for (int i = 0; i < REGSIZE; i++) { sprintf(stbuf, "registers.reg(%d)", i); sc_trace(tf, registers.rfile[i], stbuf); } for (int i = 0; i < RAMSIZE; i++) { sprintf(stbuf, "memory.dmem(%d)", i); sc_trace(tf, dmem.ramfile[i], stbuf); } for (int i = 0; i < ROMSIZE; i++) { sprintf(stbuf, "memory.imem(%d)", i); sc_trace(tf, imem.romfile[i], stbuf); } // SIMULATION int sim_time = 500; if (argc == 2) sim_time = atoi(argv[1]); sc_start(sim_time, SC_NS); sc_close_vcd_trace_file(tf); dmem.ram_dump("mips_ram.dump"); return 0; }