u32 vcd_disable_clock(struct vcd_dev_ctxt_type *p_dev_ctxt)
{
u32 rc = VCD_S_SUCCESS;
if (p_dev_ctxt->e_pwr_clk_state == VCD_PWRCLK_STATE_OFF) {
VCD_MSG_ERROR("vcd_disable_clock(): Already in state "
"VCD_PWRCLK_STATE_OFF\n");
vcd_assert();
rc = VCD_ERR_FAIL;
} else if (p_dev_ctxt->e_pwr_clk_state == VCD_PWRCLK_STATE_ON_CLOCKED ||
p_dev_ctxt->e_pwr_clk_state == VCD_PWRCLK_STATE_ON_CLOCKGATED) {
p_dev_ctxt->n_active_clnts--;
if (!p_dev_ctxt->n_active_clnts) {
if (!res_trk_disable_clocks())
rc = VCD_ERR_FAIL;
p_dev_ctxt->e_pwr_clk_state =
VCD_PWRCLK_STATE_ON_NOTCLOCKED;
p_dev_ctxt->n_curr_perf_lvl = 0;
}
}
return rc;
}
u32 vcd_gate_clock(struct vcd_dev_ctxt *dev_ctxt)
{
u32 rc = VCD_S_SUCCESS;
if (dev_ctxt->pwr_clk_state == VCD_PWRCLK_STATE_OFF ||
dev_ctxt->pwr_clk_state == VCD_PWRCLK_STATE_ON_NOTCLOCKED) {
VCD_MSG_ERROR("%s(): Clk is Off or Not Clked yet\n", __func__);
rc = VCD_ERR_FAIL;
} else if (dev_ctxt->pwr_clk_state == VCD_PWRCLK_STATE_ON_CLOCKGATED)
rc = VCD_S_SUCCESS;
else if (res_trk_disable_clocks())
dev_ctxt->pwr_clk_state = VCD_PWRCLK_STATE_ON_CLOCKGATED;
else
rc = VCD_ERR_FAIL;
return rc;
}
u32 vcd_gate_clock(struct vcd_dev_ctxt_type *p_dev_ctxt)
{
u32 rc = VCD_S_SUCCESS;
if (p_dev_ctxt->e_pwr_clk_state == VCD_PWRCLK_STATE_OFF ||
p_dev_ctxt->e_pwr_clk_state == VCD_PWRCLK_STATE_ON_NOTCLOCKED) {
VCD_MSG_ERROR("%s(): Clk is Off or Not Clked yet \n", __func__);
vcd_assert();
return VCD_ERR_FAIL;
}
if (p_dev_ctxt->e_pwr_clk_state == VCD_PWRCLK_STATE_ON_CLOCKGATED)
return rc;
if (res_trk_disable_clocks())
p_dev_ctxt->e_pwr_clk_state = VCD_PWRCLK_STATE_ON_CLOCKGATED;
else
rc = VCD_ERR_FAIL;
return rc;
}
static u32 res_trk_shutdown_vidc(void)
{
mutex_lock(&resource_context.lock);
if (resource_context.clock_enabled) {
mutex_unlock(&resource_context.lock);
VCDRES_MSG_LOW("\n Calling CLK disable in Power Down\n");
res_trk_disable_clocks();
mutex_lock(&resource_context.lock);
}
res_trk_put_clk();
if (resource_context.footswitch) {
if (regulator_disable(resource_context.footswitch))
VCDRES_MSG_ERROR("Regulator disable failed\n");
regulator_put(resource_context.footswitch);
resource_context.footswitch = NULL;
}
if (pm_runtime_put(resource_context.device) < 0)
VCDRES_MSG_ERROR("Error : pm_runtime_put failed");
mutex_unlock(&resource_context.lock);
return true;
}
static u32 res_trk_disable_pwr_rail(void)
{
int rc = -1;
mutex_lock(&resource_context.lock);
if (resource_context.clock_enabled) {
mutex_unlock(&resource_context.lock);
VCDRES_MSG_LOW("\n Calling CLK disable in Power Down\n");
res_trk_disable_clocks();
mutex_lock(&resource_context.lock);
}
if (!resource_context.rail_enabled) {
mutex_unlock(&resource_context.lock);
return false;
}
resource_context.rail_enabled = 0;
rc = clk_reset(resource_context.pclk, CLK_RESET_ASSERT);
if (rc) {
VCDRES_MSG_ERROR("\n clk_reset failed %d\n", rc);
mutex_unlock(&resource_context.lock);
return false;
}
msleep(20);
rc = internal_pwr_rail_ctl(PWR_RAIL_MFC_CLK, 0);
if (rc) {
VCDRES_MSG_ERROR("\n clk_reset failed %d\n", rc);
mutex_unlock(&resource_context.lock);
return false;
}
clk_put(resource_context.hclk_div2);
clk_put(resource_context.hclk);
clk_put(resource_context.pclk);
mutex_unlock(&resource_context.lock);
return true;
}
static u32 res_trk_disable_pwr_rail(void)
{
mutex_lock(&resource_context.lock);
if (clock_enabled == 1) {
mutex_unlock(&resource_context.lock);
return true;
}
if (resource_context.clock_enabled) {
mutex_unlock(&resource_context.lock);
VCDRES_MSG_LOW("\n Calling CLK disable in Power Down\n");
res_trk_disable_clocks();
mutex_lock(&resource_context.lock);
}
clk_put(resource_context.vcodec_clk);
/*TODO: Power rail functions needs to added here*/
if (!resource_context.rail_enabled) {
mutex_unlock(&resource_context.lock);
return false;
}
resource_context.rail_enabled = 0;
mutex_unlock(&resource_context.lock);
return true;
}
u32 vcd_disable_clock(struct vcd_dev_ctxt *dev_ctxt)
{
u32 rc = VCD_S_SUCCESS;
if (dev_ctxt->pwr_clk_state == VCD_PWRCLK_STATE_OFF) {
VCD_MSG_ERROR("vcd_disable_clock(): Already in state "
"VCD_PWRCLK_STATE_OFF\n");
rc = VCD_ERR_FAIL;
} else if (dev_ctxt->pwr_clk_state == VCD_PWRCLK_STATE_ON_CLOCKED ||
dev_ctxt->pwr_clk_state == VCD_PWRCLK_STATE_ON_CLOCKGATED) {
dev_ctxt->active_clnts--;
if (!dev_ctxt->active_clnts) {
if (!res_trk_disable_clocks())
rc = VCD_ERR_FAIL;
dev_ctxt->pwr_clk_state =
VCD_PWRCLK_STATE_ON_NOTCLOCKED;
dev_ctxt->curr_perf_lvl = 0;
}
}
return rc;
}
//static u32 res_trk_disable_pwr_rail(void)
static u32 res_trk_disable_videocore(void)
/* 20110511 Y.Yagami -S vidc: vdec: Generate output done in reconfig. */
{
int rc = -1;
mutex_lock(&resource_context.lock);
#ifdef PATCH0330
#else
if (resource_context.clock_enabled) {
mutex_unlock(&resource_context.lock);
VCDRES_MSG_LOW("\n Calling CLK disable in Power Down\n");
res_trk_disable_clocks();
mutex_lock(&resource_context.lock);
}
#endif /* PATCH0330 */
if (!resource_context.rail_enabled) {
mutex_unlock(&resource_context.lock);
return false;
}
#ifdef PATCH0330
if (!resource_context.clock_enabled &&
resource_context.pclk &&
resource_context.hclk &&
resource_context.hclk_div2) {
VCDRES_MSG_LOW("\nEnabling clk before disabling pwr rail\n");
/* 20110511 Y.Yagami CHG-S msm: vidc: Fix video core clock power up/down sequence */
// clk_set_rate(resource_context.hclk,
// mfc_clk_freq_table[0]);
if (clk_set_rate(resource_context.hclk,
mfc_clk_freq_table[0])) {
VCDRES_MSG_ERROR("\n pwr_rail_disable:"
" set clk rate failed\n");
goto bail_out;
}
/* 20110511 Y.Yagami CHG-E msm: vidc: Fix video core clock power up/down sequence */
if (clk_enable(resource_context.pclk)) {
VCDRES_MSG_ERROR("vidc pclk Enable failed\n");
goto bail_out;
}
if (clk_enable(resource_context.hclk)) {
VCDRES_MSG_ERROR("vidc hclk Enable failed\n");
goto disable_pclk;
}
if (clk_enable(resource_context.hclk_div2)) {
VCDRES_MSG_ERROR("vidc hclk_div2 Enable failed\n");
goto disable_hclk;
}
} else {
VCDRES_MSG_ERROR("\ndisabling pwr rail: Enabling clk failed\n");
goto bail_out;
}
#endif /* PATCH0330 */
resource_context.rail_enabled = 0;
rc = clk_reset(resource_context.pclk, CLK_RESET_ASSERT);
if (rc) {
VCDRES_MSG_ERROR("\n clk_reset failed %d\n", rc);
mutex_unlock(&resource_context.lock);
return false;
}
msleep(20);
rc = internal_pwr_rail_ctl(PWR_RAIL_MFC_CLK, 0);
if (rc) {
VCDRES_MSG_ERROR("\n clk_reset failed %d\n", rc);
mutex_unlock(&resource_context.lock);
return false;
}
#ifdef PATCH0330
clk_disable(resource_context.pclk);
clk_disable(resource_context.hclk);
clk_disable(resource_context.hclk_div2);
#endif /* PATCH0330 */
clk_put(resource_context.hclk_div2);
clk_put(resource_context.hclk);
clk_put(resource_context.pclk);
#ifdef PATCH0330
resource_context.hclk_div2 = NULL;
resource_context.hclk = NULL;
resource_context.pclk = NULL;
#endif /* PATCH0330 */
mutex_unlock(&resource_context.lock);
return true;
#ifdef PATCH0330
disable_hclk:
clk_disable(resource_context.hclk);
disable_pclk:
clk_disable(resource_context.pclk);
bail_out:
if (resource_context.pclk) {
clk_put(resource_context.pclk);
resource_context.pclk = NULL;
}
if (resource_context.hclk) {
clk_put(resource_context.hclk);
resource_context.hclk = NULL;
}
if (resource_context.hclk_div2) {
clk_put(resource_context.hclk_div2);
resource_context.hclk_div2 = NULL;
}
mutex_unlock(&resource_context.lock);
return false;
#endif /* PATCH0330 */
}
