long int initdram(int board_type) { volatile immap_t *im = (volatile immap_t *)CFG_IMMR; volatile lbus83xx_t *lbc = &im->lbus; u32 msize; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; puts("Initializing\n"); /* DDR SDRAM - Main SODIMM */ msize = fixed_sdram(); /* Local Bus setup lbcr and mrtpr */ lbc->lbcr = CFG_LBC_LBCR; lbc->mrtpr = CFG_LBC_MRTPR; sync(); #ifndef CFG_8313ERDB_BROKEN_PMC if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) resume_from_sleep(); #endif puts(" DDR RAM: "); /* return total bus SDRAM size(bytes) -- DDR */ return msize; }
phys_size_t initdram(int board_type) { volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; u32 msize; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; /* DDR SDRAM */ #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) msize = fixed_sdram(); #else msize = CONFIG_SYS_DDR_SIZE << 20; #endif if (im->pmc.pmccr1 & PMCCR1_POWER_OFF){ #if !defined(CONFIG_NAND_SPL) resume_system_config(); #endif resume_from_sleep(); } /* return total bus SDRAM size(bytes) -- DDR */ return msize; }