void rfpt_init(void)
{
volatile uint16 wait;
SetWord16(CLK_RADIO_REG, 0x0089); // En BLE clk, dis BLE timer, En RFCU, RFCU div by 2
SetWord16(BLE_CNTL2_REG, 0x2000); //
SetBits16 (CLK_AMBA_REG, OTP_ENABLE, 1);
SetBits16 (CLK_AMBA_REG, HCLK_DIV, 0);
SetBits16 (TEST_CTRL_REG, ENABLE_RFPT, 1);
// Recommended settings
//set_recommended_settings();
rf_regs();
IffCalibration();
DCoffsetCalibration();
WAIT100(); // Wait 100 us to finish all DCF signals
}
void rf_reinit_func(void)
{
uint32 tmp32 = 0;
SetBits32(&tmp32, RTRIP_DELAY, 7);
SetBits32(&tmp32, TXPWRDN, 0x5);
SetBits32(&tmp32, RXPWRUP, RXPWRUP_VAL);
SetBits32(&tmp32, TXPWRUP, TXPWRUP_VAL);
SetWord32(BLE_RADIOPWRUPDN_REG, tmp32);
SetBits32(BLE_RADIOCNTL1_REG, XRFSEL, 3);
SetBits32(BLE_RWBTLECNTL_REG, SYNCERR, 0); //this must be always '0'
SetBits16(CLK_RADIO_REG, RFCU_DIV, 1); //RFCU clock must always be 8MHz!
SetBits16(CLK_RADIO_REG, RFCU_ENABLE, 1);
SetBits16(PMU_CTRL_REG, RETENTION_MODE, 0xF);
if (lp_clk_sel == LP_CLK_XTAL32)
{
//If LP clock is XTAL32 in Boost mode set XTAL32K_CUR to 1.
if (GetBits16(ANA_STATUS_REG, BOOST_SELECTED) == 0x1)
SetBits16(CLK_32K_REG, XTAL32K_CUR, 1);
}
rf_regs();
#if LUT_PATCH_ENABLED
const volatile struct LUT_CFG_struct *pLUT_CFG; // = (const volatile struct LUT_CFG_struct *)(jump_table_struct[lut_cfg_pos]);
pLUT_CFG= (const volatile struct LUT_CFG_struct *)(jump_table_struct[lut_cfg_pos]);
if (pLUT_CFG->HW_LUT_MODE)
{
SetWord16(RF_VCOCAL_CTRL_REG, vcocal_ctrl_reg_val);
}
#endif //LUT_PATCH_ENABLED
enable_rf_diag_irq(RF_DIAG_IRQ_MODE_RXTX); // This just enables the TX_EN int. RX_EN int enable status remains as it was
}
void rf_init_func(struct rwip_rf_api *api)
{
uint32 tmp32 = 0;
uint8 idx = 0;
uint8 temp_freq_tbl[EM_BLE_FREQ_TABLE_LEN];
// Initialize the RF driver API structure
api->reg_rd = rf_reg_rd;
api->reg_wr = rf_reg_wr;
api->txpwr_dbm_get = rf_txpwr_dbm_get;
//api->txpwr_max = RPL_POWER_MAX;
api->sleep = rf_sleep;
api->reset = rf_reset;
#ifdef CFG_BLE
api->isr = RADIOCNTL_Handler;
api->force_agc_enable = rf_force_agc_enable;
#endif //CFG_BLE
api->rssi_convert = rf_rssi_convert;
#ifdef CFG_BT
api->txpwr_inc = rf_txpwr_inc;
api->txpwr_dec = rf_txpwr_dec;
api->txpwr_epc_req = rf_txpwr_epc_req;
api->txpwr_cs_get = rf_txpwr_cs_get;
api->rssi_high_thr = (uint8_t)RPL_RSSI_20dB_THRHLD;
api->rssi_low_thr = (uint8_t)RPL_RSSI_60dB_THRHLD;
api->rssi_interf_thr = (uint8_t)RPL_RSSI_70dB_THRHLD;
#ifdef CFG_BTCORE_30
api->wakeup_delay = RPL_WK_UP_DELAY;
#endif //CFG_BTCORE_30
api->skew = RPL_RADIO_SKEW;
#endif //CFG_BT
// CLK_FREQ_TRIM_REG initialization was moved to main_func() in arch_main.c
// The initialization of this register is done by the Boot ROM code if a valid
// value has been written to the corresponding position in the OTP header by
// the customer.
// main_func() will write this register with a default value and the customer
// must remove this code when he has written the OTP header.
SetBits32(&tmp32, RTRIP_DELAY, 7);
SetBits32(&tmp32, TXPWRDN, 0x5);
SetBits32(&tmp32, RXPWRUP, RXPWRUP_VAL);
SetBits32(&tmp32, TXPWRUP, TXPWRUP_VAL);
SetWord32(BLE_RADIOPWRUPDN_REG,tmp32);
SetBits32(BLE_RADIOCNTL0_REG, DPCORR_EN, 0); //THIS MAY NOT BE '1', THEN WE MISS 12 BITS IN THE SYNCWORD DURING A RX BURST
SetBits32(BLE_RADIOCNTL1_REG, XRFSEL, 3);
SetBits32(BLE_CNTL2_REG, SW_RPL_SPI ,0);
SetBits32(BLE_CNTL2_REG, BB_ONLY,0);
while(idx < EM_BLE_FREQ_TABLE_LEN)
{
temp_freq_tbl[idx] = idx ;
idx++;
}
em_ble_burst_wr(&temp_freq_tbl[0], EM_BLE_FT_OFFSET, EM_BLE_FREQ_TABLE_LEN);
rf_regs();
last_temp_count = get_rc16m_count();
#if LUT_PATCH_ENABLED
pll_vcocal_LUT_InitUpdate(LUT_INIT);
#endif
rf_calibration();
}
