static void tulip_down (/*RTnet*/struct rtnet_device *rtdev)
{
long ioaddr = rtdev->base_addr;
struct tulip_private *tp = (struct tulip_private *) rtdev->priv;
rtdm_irq_disable(&tp->irq_handle);
rtdm_lock_get(&tp->lock); /* sync with IRQ handler on other cpu -JK- */
/* Disable interrupts by clearing the interrupt mask. */
outl (0x00000000, ioaddr + CSR7);
/* Stop the Tx and Rx processes. */
tulip_stop_rxtx(tp);
/* prepare receive buffers */
tulip_refill_rx(rtdev);
/* release any unconsumed transmit buffers */
tulip_clean_tx_ring(tp);
/* 21040 -- Leave the card in 10baseT state. */
if (tp->chip_id == DC21040)
outl (0x00000004, ioaddr + CSR13);
if (inl (ioaddr + CSR6) != 0xffffffff)
tp->stats.rx_missed_errors += inl (ioaddr + CSR8) & 0xffff;
rtdm_lock_put(&tp->lock);
rtdm_irq_enable(&tp->irq_handle);
rtdev->if_port = tp->saved_if_port;
/* Leave the driver in snooze, not sleep, mode. */
tulip_set_power_state (tp, 0, 1);
}
int demo_open_rt(struct rtdm_dev_context *context,
rtdm_user_info_t *user_info,
int oflags)
{
struct demodrv_context *my_context;
#ifdef USEMMAP
unsigned long vaddr;
#endif
int dev_id = context->device->device_id;
int ret;
// get the context for our driver - used to store driver info
my_context = (struct demodrv_context *)context->dev_private;
#ifdef USEMMAP
// allocate and prepare memory for our buffer
my_context->buf = kmalloc(BUFFER_SIZE, GFP_KERNEL);
/* mark pages reserved so that remap_pfn_range works */
for (vaddr = (unsigned long)my_context->buf;
vaddr < (unsigned long)my_context->buf + BUFFER_SIZE;
vaddr += PAGE_SIZE)
SetPageReserved(virt_to_page(vaddr));
// write some test value to the start of our buffer
*(int *)my_context->buf = 1234;
my_context->mapped_user_addr = NULL;
#endif
// we also have an interrupt handler:
#ifdef TIMERINT
ret = rtdm_irq_request(&my_context->irq_handle, TIMER_INT, demo_interrupt,
0, context->device->proc_name, my_context);
#else
ret = rtdm_irq_request(&my_context->irq_handle, PAR_INT, demo_interrupt,
0, context->device->proc_name, my_context);
#endif
if (ret < 0)
return ret;
/* IPC initialisation - cannot fail with used parameters */
rtdm_lock_init(&my_context->lock);
rtdm_event_init(&my_context->irq_event, 0);
my_context->dev_id = dev_id;
my_context->irq_events = 0;
my_context->irq_event_lock = 0;
my_context->timeout = 0; // wait INFINITE
#ifndef TIMERINT
//set port to interrupt mode; pins are output
outb_p(0x10, BASEPORT + 2);
#endif
// enable interrupt in RTDM
rtdm_irq_enable(&my_context->irq_handle);
return 0;
}
static int rt2x00_dev_radio_on(struct _rt2x00_device * device) {
struct _rt2x00_pci *rt2x00pci = rt2x00_priv(device);
u32 reg = 0x00000000;
int retval;
if(rt2x00_pci_alloc_rings(device))
goto exit_fail;
rt2x00_clear_ring(rt2x00pci, &rt2x00pci->rx);
rt2x00_clear_ring(rt2x00pci, &rt2x00pci->tx);
rt2x00_init_ring_register(rt2x00pci);
if(rt2x00_init_registers(rt2x00pci))
goto exit_fail;
rt2x00_init_write_mac(rt2x00pci, device->rtnet_dev);
if(rt2x00_init_bbp(rt2x00pci))
goto exit_fail;
/*
* Clear interrupts.
*/
rt2x00_register_read(rt2x00pci, CSR7, ®);
rt2x00_register_write(rt2x00pci, CSR7, reg);
/* Register rtdm-irq */
retval = rtdm_irq_request(&rt2x00pci->irq_handle,
device->rtnet_dev->irq,
rt2x00_interrupt, 0,
device->rtnet_dev->name,
device->rtnet_dev);
/*
* Enable interrupts.
*/
rt2x00_register_read(rt2x00pci, CSR8, ®);
rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, 0);
rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0);
rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0);
rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0);
rt2x00_set_field32(®, CSR8_RXDONE, 0);
rt2x00_register_write(rt2x00pci, CSR8, reg);
rtdm_irq_enable(&rt2x00pci->irq_handle);
return 0;
exit_fail:
rt2x00_pci_free_rings(device);
return -ENOMEM;
}
static int
scc_enet_start_xmit(struct rtskb *skb, struct rtnet_device *rtdev)
{
struct scc_enet_private *cep = (struct scc_enet_private *)rtdev->priv;
volatile cbd_t *bdp;
rtdm_lockctx_t context;
RT_DEBUG(__FUNCTION__": ...\n");
/* Fill in a Tx ring entry */
bdp = cep->cur_tx;
#ifndef final_version
if (bdp->cbd_sc & BD_ENET_TX_READY) {
/* Ooops. All transmit buffers are full. Bail out.
* This should not happen, since cep->tx_busy should be set.
*/
rtdm_printk("%s: tx queue full!.\n", rtdev->name);
return 1;
}
#endif
/* Clear all of the status flags.
*/
bdp->cbd_sc &= ~BD_ENET_TX_STATS;
/* If the frame is short, tell CPM to pad it.
*/
if (skb->len <= ETH_ZLEN)
bdp->cbd_sc |= BD_ENET_TX_PAD;
else
bdp->cbd_sc &= ~BD_ENET_TX_PAD;
/* Set buffer length and buffer pointer.
*/
bdp->cbd_datlen = skb->len;
bdp->cbd_bufaddr = __pa(skb->data);
/* Save skb pointer.
*/
cep->tx_skbuff[cep->skb_cur] = skb;
cep->stats.tx_bytes += skb->len;
cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK;
/* Prevent interrupts from changing the Tx ring from underneath us. */
// *** RTnet ***
#if 0
rtdm_irq_disable(&cep->irq_handle);
rtdm_lock_get(&cep->lock);
#else
rtdm_lock_get_irqsave(&cep->lock, context);
#endif
/* Get and patch time stamp just before the transmission */
if (skb->xmit_stamp)
*skb->xmit_stamp = cpu_to_be64(rtdm_clock_read() + *skb->xmit_stamp);
/* Push the data cache so the CPM does not get stale memory
* data.
*/
flush_dcache_range((unsigned long)(skb->data),
(unsigned long)(skb->data + skb->len));
/* Send it on its way. Tell CPM its ready, interrupt when done,
* its the last BD of the frame, and to put the CRC on the end.
*/
bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | BD_ENET_TX_TC);
#if 0
dev->trans_start = jiffies;
#endif
/* If this was the last BD in the ring, start at the beginning again.
*/
if (bdp->cbd_sc & BD_ENET_TX_WRAP)
bdp = cep->tx_bd_base;
else
bdp++;
if (bdp->cbd_sc & BD_ENET_TX_READY) {
rtnetif_stop_queue(rtdev);
cep->tx_full = 1;
}
cep->cur_tx = (cbd_t *)bdp;
// *** RTnet ***
#if 0
rtdm_lock_put(&cep->lock);
rtdm_irq_enable(&cep->irq_handle);
#else
rtdm_lock_put_irqrestore(&cep->lock, context);
#endif
return 0;
}
static int rtdm_my_isr(rtdm_irq_t *irq_context)
{
MY_DEV *up=rtdm_irq_get_arg(irq_context,MY_DEV);
up->systime1 = rtdm_clock_read();
up->timeout = up->systime1 - up->systime;
printk("Interrupt Latency=%dl\n",up->timeout);
up->systime1=0;
up->systime=0;
unsigned int iir,lsr;
unsigned int type;
irqreturn_t ret=IRQ_NONE;
int err;
int max_count = 256;
rtdm_lockctx_t context1;
printk("I am in rtdm_my_isr......!!!\n");
printk("Local struct up=%x\n",up);
err = rtdm_irq_disable(&up->irq_handle);
if(err<0)
rtdm_printk("error in rtdm_irq_enable\n");
rtdm_lock_get_irqsave(&up->lock,context1);
do{
iir = serial_in(up,UART_IIR);
if(iir & UART_IIR_NO_INT)
break;
ret=IRQ_HANDLED;
lsr = serial_in(up,UART_LSR);
type = iir & 0x3e;
switch(type)
{
case UART_IIR_THRI:
printk("type of int:UART_IIR_THRI\n");
transmit_chars(up,lsr);
rtdm_event_signal(&up->w_event_tx);
break;
case UART_IIR_RX_TIMEOUT:
/*FALLTHROUGH*/
case UART_IIR_RDI:
printk("type of int:UART_IIR_RDI\n");
serial_omap_rdi(up,lsr);
rtdm_event_signal(&up->w_event_rx);
break;
case UART_IIR_RLSI:
printk("type of int:UART_IIR_RLSI\n");
// serial_omap_rlsi(up,lsr);
break;
case UART_IIR_CTS_RTS_DSR:
break;
case UART_IIR_XOFF:
/*simpleThrough*/
default:
break;
}
}while(!(iir & UART_IIR_NO_INT) && max_count--);
rtdm_lock_put_irqrestore(&up->lock,context1);
err = rtdm_irq_enable(&up->irq_handle);
if(err<0)
rtdm_printk("error in rtdm_irq_enable\n");
printk("rtdm_irq ended\n");
up->systime = rtdm_clock_read();
return RTDM_IRQ_HANDLED;
}
static void serial_omap_set_termios(MY_DEV *up, unsigned int request)
{
int val;
unsigned char cval = 0;
unsigned int baud, quot;
rtdm_lockctx_t context1;
int err;
printk("serial_omap_set_termios\n");
printk("Local struct up=%x\n",up);
printk("request=%x\n",request);
val=request & 0x03;
printk("val=%x",val);
switch(val)
{
case CS5_1:
printk("CS5\n");
cval = UART_LCR_WLEN5;
break;
case CS6_1:
printk("CS6\n");
cval = UART_LCR_WLEN6;
break;
case CS7_1:
printk("CS7\n");
cval = UART_LCR_WLEN7;
break;
default:
case CS8_1:
printk("CS8\n");
cval = UART_LCR_WLEN8;
break;
}
if(request & 0x04)
{ printk("set two stop bits\n");
cval |= UART_LCR_STOP;
}
if(request & 0x08)
{ printk("set even patity\n");
cval |= UART_LCR_PARITY;
}
if(request & 0x10)
{ printk("set odd parity\n");
cval |= UART_LCR_EPAR;
}
val=request & 0x60;
val = val >> 5;
switch(val)
{
case BAUD_4800:
printk("BAUD_4800\n");
baud = 4800;
break;
case BAUD_9600:
printk("BAUD_9600\n");
baud = 9600;
break;
case BAUD_115200:
printk("BAUD_115200\n");
baud = 115200;
default:
printk("default\n");
baud = 9600;
}
// baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
quot = serial_omap_get_divisor(up, baud);//for getting dll and dlh register value
printk("serial_omap_get_divisor=%d\n",quot);
up->calc_latency = (USEC_PER_SEC * up->fifosize) / (baud / 8);
up->latency = up->calc_latency;
up->dll = quot & 0xff;
up->dlh = quot >> 8;
up->mdr1 = UART_OMAP_MDR1_DISABLE;
up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | UART_FCR_ENABLE_FIFO;
err = rtdm_irq_disable(&up->irq_handle);
if(err<0)
rtdm_printk("error in rtdm_irq_enable\n");
rtdm_lock_get_irqsave(&up->lock,context1);
up->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
// if (termios->c_iflag & INPCK)
// up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; //Frame error indicator, Parity error indicator
//
// if (termios->c_iflag & (BRKINT | PARMRK))
// up->port.read_status_mask |= UART_LSR_BI; //Break interrupt indicator
up->ignore_status_mask = 0;
//this should be passed from user space
// if (termios->c_iflag & IGNBRK) // IGNBRK Ignore BREAK condition on input.
// {
printk("Ignore Break condition on input\n");
up->ignore_status_mask |= UART_LSR_BI;
// }
up->ier &= ~UART_IER_MSI;
serial_out(up, UART_IER, up->ier);
printk("Enable interrupt\n");
serial_out(up, UART_LCR, cval); //writing the setting to Line control register /* reset DLAB */
up->lcr = cval; //saving the setting of line control register
up->scr = OMAP_UART_SCR_TX_EMPTY;
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_out(up, UART_DLL, 0);
serial_out(up, UART_DLM, 0);
serial_out(up, UART_LCR, 0);
//***********************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); //config to mode B
up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;//value of efr register without enhance function write enable bit
up->efr &= ~UART_EFR_SCD; //remove special character detect enable
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); //writing to EFR register with enhance function write enable bit
//************************************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); //config to mode A
up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; //value to TCRTLR=0(No action) if 1 then we can enable TCR and TLR
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); //writing value to the MCR with TCRTLR enable
/* FIFO ENABLE, DMA MODE */
up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; //enable the granularity of 1 for trigger RX level
//*******************************************************************
/* Set receive FIFO threshold to 16 characters and
* transmit FIFO threshold to 16 spaces
*/
up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; // dont set RX_FIFO_TRIG to 60 character
up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; //dont set TX_FIFO_TRIG to 56 character
up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | UART_FCR_ENABLE_FIFO; //Rx fifo trigger at 16 character | Tx fifo trigger at 32 char | FIFO_EN
serial_out(up, UART_FCR, up->fcr); //write to FCR
//********************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); //config to mode B
serial_out(up, UART_OMAP_SCR, up->scr); //writing to SCR(supplementary control register)
//*******************************************************************
/* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); //config mode A
serial_out(up, UART_MCR, up->mcr); //writing to MCR without TCRTLR
//*******************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); //config mode B
serial_out(up, UART_EFR, up->efr); //writing to EFR register without special character detect enable
//*******************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); //config mode A
/* Protocol, Baud Rate, and Interrupt Settings */
if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) //
serial_omap_mdr1_errataset(up, up->mdr1);
else
serial_out(up, UART_OMAP_MDR1, up->mdr1);
//********************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); //config mode B
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); //writing to EFR register with special character
serial_out(up, UART_LCR, 0); //writing line control register
serial_out(up, UART_IER, 0); //writing to IER
//********************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_DLL, up->dll); /* LS of divisor */
serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
serial_out(up, UART_LCR, 0);
serial_out(up, UART_IER, up->ier);
//********************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_EFR, up->efr);
serial_out(up, UART_LCR, cval);
if (baud > 230400 && baud != 3000000)
{ printk("baud > 230400\n");
up->mdr1 = UART_OMAP_MDR1_13X_MODE;
}
else
{ printk("baud < 230400\n");
up->mdr1 = UART_OMAP_MDR1_16X_MODE;
}
if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
{ printk("up->errata condition true\n");
serial_omap_mdr1_errataset(up, up->mdr1);
}
else
{ printk("up->errata condition false\n");
serial_out(up, UART_OMAP_MDR1, up->mdr1);
}
//***********************************************************************
/* Configure flow control */
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
/* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
// serial_out(up, UART_XON1, termios->c_cc[VSTART]);
// serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
/* Enable access to TCR/TLR */
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);//TCR trasmission control register value 0xFF
//no hardware control
up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
serial_out(up, UART_MCR, up->mcr); //write to MCR
printk("write to UART_MCR\n");
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); //write to LCR for switching to config mode B
printk("Switch to config mode B\n");
serial_out(up, UART_EFR, up->efr); //write to EFR
printk("write to EFR register\n");
serial_out(up, UART_LCR, up->lcr); //write to LCR
printk("write to LCR\n");
rtdm_lock_put_irqrestore(&up->lock,context1);
err = rtdm_irq_enable(&up->irq_handle);
if(err<0)
rtdm_printk("error in rtdm_irq_enable\n");
printk("serial_omap_set_termios end\n");
}
