int nfp_hwmon_read_sensor(struct nfp_cpp *cpp, enum nfp_nsp_sensor_id id, long *val) { struct nfp_sensors s; struct nfp_nsp *nsp; int ret; nsp = nfp_nsp_open(cpp); if (!nsp) return -EIO; ret = nfp_nsp_read_sensors(nsp, BIT(id), &s, sizeof(s)); nfp_nsp_close(nsp); if (ret < 0) return ret; switch (id) { case NFP_SENSOR_CHIP_TEMPERATURE: *val = rte_le_to_cpu_32(s.chip_temp); break; case NFP_SENSOR_ASSEMBLY_POWER: *val = rte_le_to_cpu_32(s.assembly_power); break; case NFP_SENSOR_ASSEMBLY_12V_POWER: *val = rte_le_to_cpu_32(s.assembly_12v_power); break; case NFP_SENSOR_ASSEMBLY_3V3_POWER: *val = rte_le_to_cpu_32(s.assembly_3v3_power); break; default: return -EINVAL; } return 0; }
static int vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) { struct rte_eth_conf port_conf = dev->data->dev_conf; struct vmxnet3_hw *hw = dev->data->dev_private; uint32_t mtu = dev->data->mtu; Vmxnet3_DriverShared *shared = hw->shared; Vmxnet3_DSDevRead *devRead = &shared->devRead; uint32_t i; int ret; shared->magic = VMXNET3_REV1_MAGIC; devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM; /* Setting up Guest OS information */ devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ? VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64; devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; devRead->misc.driverInfo.vmxnet3RevSpt = 1; devRead->misc.driverInfo.uptVerSpt = 1; devRead->misc.mtu = rte_le_to_cpu_32(mtu); devRead->misc.queueDescPA = hw->queueDescPA; devRead->misc.queueDescLen = hw->queue_desc_len; devRead->misc.numTxQueues = hw->num_tx_queues; devRead->misc.numRxQueues = hw->num_rx_queues; /* * Set number of interrupts to 1 * PMD disables all the interrupts but this is MUST to activate device * It needs at least one interrupt for link events to handle * So we'll disable it later after device activation if needed */ devRead->intrConf.numIntrs = 1; devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; for (i = 0; i < hw->num_tx_queues; i++) { Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i]; vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i]; tqd->ctrl.txNumDeferred = 0; tqd->ctrl.txThreshold = 1; tqd->conf.txRingBasePA = txq->cmd_ring.basePA; tqd->conf.compRingBasePA = txq->comp_ring.basePA; tqd->conf.dataRingBasePA = txq->data_ring.basePA; tqd->conf.txRingSize = txq->cmd_ring.size; tqd->conf.compRingSize = txq->comp_ring.size; tqd->conf.dataRingSize = txq->data_ring.size; tqd->conf.intrIdx = txq->comp_ring.intr_idx; tqd->status.stopped = TRUE; tqd->status.error = 0; memset(&tqd->stats, 0, sizeof(tqd->stats)); } for (i = 0; i < hw->num_rx_queues; i++) { Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i]; vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA; rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA; rqd->conf.compRingBasePA = rxq->comp_ring.basePA; rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size; rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size; rqd->conf.compRingSize = rxq->comp_ring.size; rqd->conf.intrIdx = rxq->comp_ring.intr_idx; rqd->status.stopped = TRUE; rqd->status.error = 0; memset(&rqd->stats, 0, sizeof(rqd->stats)); } /* RxMode set to 0 of VMXNET3_RXM_xxx */ devRead->rxFilterConf.rxMode = 0; /* Setting up feature flags */ if (dev->data->dev_conf.rxmode.hw_ip_checksum) devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM; if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { ret = vmxnet3_rss_configure(dev); if (ret != VMXNET3_SUCCESS) return ret; devRead->misc.uptFeatures |= VMXNET3_F_RSS; devRead->rssConfDesc.confVer = 1; devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf); devRead->rssConfDesc.confPA = hw->rss_confPA; } vmxnet3_dev_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); vmxnet3_write_mac(hw, hw->perm_addr); return VMXNET3_SUCCESS; }
u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg) { return rte_le_to_cpu_32(rte_read32((u8 *)hw->mmio + reg)); }