void BASEXTCmd()
{
w32 where;
struct BAS_PFENTRY *p=ext_list;
where=(w32)((char*)pc-(char*)theROM-2);
/*printf("BASIC EXTENSION\n");*/
while(p)
{
if (where==p->code_addr) break;
p=p->link;
}
if (!p)
{
rts();
printf("problem with basic extension\n");
return;
}
reg[0]=(p->command)();
rts();
}
static void a_txint(struct pi_local *lp)
{
int cmd;
unsigned long flags;
save_flags(flags);
cli();
cmd = CTL + lp->base;
switch (lp->tstate) {
case IDLE:
/* Transmitter idle. Find a frame for transmission */
if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
rts(lp, OFF);
restore_flags(flags);
return;
}
/* If a buffer to send, we drop thru here */
case DEFER:
/* we may have deferred prev xmit attempt */
/* Check DCD - debounce it
* See Intel Microcommunications Handbook, p2-308
*/
wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
lp->tstate = DEFER;
tdelay(lp, 100);
/* defer until DCD transition or timeout */
wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
restore_flags(flags);
return;
}
if (random() > lp->persist) {
lp->tstate = DEFER;
tdelay(lp, lp->slotime);
restore_flags(flags);
return;
}
/* Assert RTS early minimize collision window */
wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
rts(lp, ON); /* Transmitter on */
lp->tstate = ST_TXDELAY;
tdelay(lp, lp->txdelay);
restore_flags(flags);
return;
default:
break;
} /* end switch(lp->state) */
restore_flags(flags);
} /*a_txint */
void DrvClose(void)
{
char *f;
struct DRV *driver;
int ix;
w32 saved_regs[16];
if((long)((Ptr)gPC-(Ptr)theROM)-2 != DEV_CLOSE_ADDR)
{
exception=4;
extraFlag=true;
nInst2=nInst;
nInst=0;
return;
}
//save_regs(saved_regs);
f=a0addr(false);
if(f==nil)
{
*reg=QERR_NO; /* overflow */
rts();
return;
}
#if 0
if (DGET_ID(f)!=DRV_ID)
{
reg[0]= QERR_NO;
rts();
return;
}
#endif
driver=dget_drv(); /*&Drivers[DGET_DRV(f)];*/
ix=driver-Drivers;
if (driver==0)
{
printf("possible driver problem ??\n");
return;
}
(*(driver->close))(ix,DGET_PRIV(f));
QLvector(0xc2,20000l);
//restore_regs(saved_regs);
rts();
}
void WriteIPC(void) /* ROM patch: writing to IPC */
{
/*printf("write IPC\n");*/
if((Ptr)gPC-(Ptr)theROM-2==IPCW_CMD_ADDR)
{
rts();
if(IPCW_n--) IPCW_buff[IPCW_p++]=(uw8)(*reg);
else
{
IPC_com=(short)(*reg)&15;
if(IPC_com!=1 && IPC_com!=8) debug2("Bad IPC Command : ",IPC_com);
IPCW_n=IPC_len[IPC_com];
IPCW_p=0;
}
if(!IPCW_n) DoIPCCommand(IPC_com);
}
else
{
exception=4;
extraFlag=true;
nInst2=nInst;
nInst=0;
}
}
void ReadIPC(void) /* ROM patch: reading from IPC */
{
if((Ptr)gPC-(Ptr)theROM-2==IPCR_CMD_ADDR)
{
/*printf("ReadIPC\n");*/
rts();
if(IPCR_n>0)
{
asciiChar=IPCR_ascii[IPCR_p];
/*printf("ReadIPC: asciiChar %d\n",asciiChar);*/
reg[1]=IPCR_buff[IPCR_p++];
IPCR_n--;
}
else reg[1]=0;
}
else
{
exception=4;
extraFlag=true;
nInst2=nInst;
nInst=0;
}
}
void DrvIO(void)
{
char *f;
struct DRV *driver;
int ix;
if((long)((Ptr)gPC-(Ptr)theROM)-2 != DEV_IO_ADDR)
{
exception=4;
extraFlag=true;
nInst2=nInst;
nInst=0;
return;
}
f=a0addr(false);
if(f==nil)
{
*reg=QERR_NO; /* overflow */
rts();
return;
}
#if 0
if (DGET_ID(f)!=DRV_ID)
{
reg[0]= QERR_NO;
rts();
return;
}
#endif
driver=dget_drv(); /*&Drivers[DGET_DRV(f)];*/
ix=driver-Drivers;
if (driver==0)
{
printf("possible driver problem ??\n");
return;
}
(*(driver->io))(ix,DGET_PRIV(f));
rts();
}
bool Set(VString rect, const int rx=0, const int ry=0){ Null();
VString vl, vr, vt, vd; unsigned char *ln;
vl=PartLine(rect, rect, ",");
vr=PartLine(rect, rect, ",");
vt=PartLine(rect, rect, ",");
vd=PartLine(rect, rect, ",");
if(!vl || !vr || !vt || !vd || rect) return 0;
dspacev(vl, 3); dspacev(vr, 3); dspacev(vt, 3); dspacev(vd, 3);
left=stoi(vl); if(left<0){ left*=-1; set|=MRECT_LM; }// if(m) set|=MRECT_LM;
ln=vl; if(rts(vl.endu(), '%', ln)){ set|=MRECT_LP; }
right=stoi(vr); if(right<0){ right*=-1; set|=MRECT_RM; }// if(m) set|=MRECT_LM;
ln=vr; if(rts(vr.endu(), '%', ln)){ set|=MRECT_RP; }
top=stoi(vt); if(top<0){ top*=-1; set|=MRECT_TM; }// if(m) set|=MRECT_LM;
ln=vt; if(rts(vt.endu(), '%', ln)){ set|=MRECT_TP; }
bottom=stoi(vd); if(bottom<0){ bottom*=-1; set|=MRECT_BM; }// if(m) set|=MRECT_LM;
ln=vd; if(rts(vd.endu(), '%', ln)){ set|=MRECT_BP; }
/*
MString tmp; int pos=0, lpos=0, m=0;
//block one
if(!rts(rect, ',', pos)){Null(); return 0;}
tmp=rect.Mid(lpos, pos-lpos); dspacea(tmp, 3); if(tmp[0]=='-'){m=1; tmp=tmp.Mid(1);} left=stoi(tmp); lpos=0; if(rts(tmp, '$', lpos)){left=rx-left; set|=1;} if(left<0){left*=-1; set|=1;} if(m)set|=1; lpos=0; if(rts(tmp, '%', lpos)){set|=2;}
lpos=++pos; m=0;
//block two
if(!rts(rect, ',', pos)){Null(); return 0;}
tmp=rect.Mid(lpos, pos-lpos); dspacea(tmp, 3); if(tmp[0]=='-'){m=1; tmp=tmp.Mid(1);} top=stoi(tmp); lpos=0; if(rts(tmp, '$', lpos)){top=ry-top; set|=4;} if(top<0){top*=-1; set|=4;} if(m)set|=4; lpos=0; if(rts(tmp, '%', lpos)){set|=8;}
lpos=++pos; m=0;
//block three
if(!rts(rect, ',', pos)){Null(); return 0;}
tmp=rect.Mid(lpos, pos-lpos); dspacea(tmp, 3); if(tmp[0]=='-'){m=1; tmp=tmp.Mid(1);} right=stoi(tmp); lpos=0; if(rts(tmp, '$', lpos)){right=rx-right; set|=16;} if(right<0){right*=-1; set|=16;} if(m)set|=16; lpos=0; if(rts(tmp, '%', lpos)){set|=32;}
lpos=++pos; m=0;
//block four
if(rts(rect, ',', pos)){Null(); return 0;}
tmp=rect.Mid(lpos, pos-lpos); dspacea(tmp, 3); if(tmp[0]=='-'){m=1; tmp=tmp.Mid(1);} bottom=stoi(tmp); lpos=0; if(rts(tmp, '$', lpos)){bottom=ry-bottom; set|=64;} if(bottom<0){bottom*=-1; set|=64;} if(m)set|=64; lpos=0; if(rts(tmp, '%', lpos)){set|=128;}
lpos=++pos; */
return 1;
}
void UseIPC(void) /* ROM patch: executing IPC command */
{
if((Ptr)gPC-(Ptr)theROM-2==IPC_CMD_ADDR)
{ if(IPC_Command()) rts();
else table[code=0x40e7]();
}
else
{ exception=4;
extraFlag=true;
nInst2=nInst;
nInst=0;
}
}
/* Minerva Keyboard handling */
void KbdCmd(void) /* do IPC command */
{
/*printf("calling SX_IPCOM: d0=%d\n",reg[0]);*/
if (reg[0]==9)
{
*((char*)reg+4+RBO)=KeyRow(ReadByte(aReg[3]+3));
WriteLong(aReg[7],ReadLong(aReg[7])+2);
}
/*printf("returning d1=%x\n",reg[1]);*/
rts();
}
int main()
{
// capture output of foo in a string
std::string str ;
{
redirect_to_string rts(std::cout) ; // redirect output to stringbuf
foo(23) ; // call foo; output from foo goes to the stringbuf
str = rts.str() ; // copy contents from he stringbuf into our string
str.pop_back() ; // remove the new-line at the end (if required)
// note: destructor of rts will restore the original streambuf
}
std::cout << "string contains: '" << str << "'\n" ;
}
static char * RTS1() {
CPU *c = getCPU();
c->PC = 0xCFEE;
uint16_t address = 0xABAB;
OP_CODE_INFO *o1 = getOP_CODE_INFO(0,address,modeImmediate);
jsr(c,o1);
OP_CODE_INFO *o2 = getOP_CODE_INFO(0,0,modeImmediate);
rts(c,o2);
mu_assert("RTS1 err, PC != 0xCFEE", c->PC == 0xCFEE);
freeOP_CODE_INFO(o1);
freeOP_CODE_INFO(o2);
free(c);
return 0;
}
bool SetXY(VString rect, const int rx=0, const int ry=0){ Null();
VString vl, vr, vt, vd; unsigned char *ln;
vl=PartLine(rect, rect, ",");
vt=PartLine(rect, rect, ",");
vr=PartLine(rect, rect, ",");
vd=PartLine(rect, rect, ",");
if(!vl || !vr || !vt || !vd || rect) return 0;
dspacev(vl, 3); dspacev(vr, 3); dspacev(vt, 3); dspacev(vd, 3);
left=stoi(vl); if(left<0){ left*=-1; set|=MRECT_LM; }// if(m) set|=MRECT_LM;
ln=vl; if(rts(vl.endu(), '%', ln)){ set|=MRECT_LP; }
right=stoi(vr); if(right<0){ right*=-1; set|=MRECT_RM; }// if(m) set|=MRECT_LM;
ln=vr; if(rts(vr.endu(), '%', ln)){ set|=MRECT_RP; }
top=stoi(vt); if(top<0){ top*=-1; set|=MRECT_TM; }// if(m) set|=MRECT_LM;
ln=vt; if(rts(vt.endu(), '%', ln)){ set|=MRECT_TP; }
bottom=stoi(vd); if(bottom<0){ bottom*=-1; set|=MRECT_BM; }// if(m) set|=MRECT_LM;
ln=vd; if(rts(vd.endu(), '%', ln)){ set|=MRECT_BP; }
return 1;
}
/* Minerva Keyboard encode routine */
void KBencCmd()
{
/*printf("KBenc called, char %c\n",asciiChar);*/
if (asciiChar)
{
reg[1]=asciiChar;
WriteLong(aReg[7],ReadLong(aReg[7])+2);
rts();
}
else /* fall through into original routine */
{
pc = (Ptr)theROM+orig_kbenc;
}
}
void QL_KeyTrans(void)
{ if((Ptr)gPC-(Ptr)theROM-2!=KEYTRANS_CMD_ADDR)
{ exception=4;
extraFlag=true;
nInst2=nInst;
nInst=0;
return;
}
if(asciiChar)
{ reg[1]=asciiChar;
asciiChar=0;
WriteLong(aReg[7],ReadLong(aReg[7])+4);
rts();
}
else table[code=KEYTRANS_OCODE]();
}
void PollCmd()
{
if((Ptr)gPC-(Ptr)theROM-2!=POLL_CMD_ADDR)
{
exception=4;
extraFlag=true;
nInst2=nInst;
nInst=0;
return;
}
#ifdef VTIME
if (poll_req>1)
printf("poll_req=%d in PollCmd()\n",poll_req);
poll_req=0;
#endif
if (isMinerva)
MReadKbd();
rts();
}
void MainWindow::newCellTest()
{
QString rts("root"), rrts("right of root and quite long at that"),
lrts("left of root");
ZZCell rt((cellID)1, 0, rts),
rrt((cellID)2, 0, rrts),
lrt((cellID)3, 0, lrts);
// QHash should make a copy for us
// since these guys will be dead soon
world.insert(1, rt);
world.insert(2, rrt);
world.insert(3, lrt);
// Construct our top-level squares
QGraphicsRectItem *rt_rect = new QGraphicsRectItem(0,0,100,20),
*rrt_rect = new QGraphicsRectItem(0,0,100,20),
*lrt_rect = new QGraphicsRectItem(0,0,100,20);
QGraphicsTextItem *rt_text = new QGraphicsTextItem(rt.getContent(), rt_rect),
*rrt_text = new QGraphicsTextItem(rrt.getContent(), rrt_rect),
*lrt_text = new QGraphicsTextItem(lrt.getContent(), lrt_rect);
rt_rect->setPos(420, 420);
rrt_rect->setPos(530, 420);
lrt_rect->setPos(310, 420);
// Add our toplevel squares to our scene
scene->addItem(rt_rect);
scene->addItem(rrt_rect);
scene->addItem(lrt_rect);
scene->update();
ui->zzViewWidget->show();
}
/////////////////////////////////////////////////////////////////////////////
// test threads
/////////////////////////////////////////////////////////////////////////////
static void ThreadsTest()
{
CPLog1D problem;
CResults results(problem.GetDimensions());
// CSPUniform sp(problem.GetDimensions());
#if 0
CPFQuadratic pf(problem.GetDimensions());
CRegression reg(results, pf);
reg.SetRefreshRate(0.1);
reg.SetLocalizationHeight(2.0);
CMERegressionMAPMax me(reg);
CDFVarianceSamples var(reg, 1);
var.SetMinSamples(problem.GetDimensions());
CSPVOptimal sp(reg, var, 0);
CArtificialExperiment artexp(problem, sp, me, results);
#else
//CCrossEntropy alt(results, 0.9);
//CSPSA alt(results);
CRSPSA alt(results);
CArtificialExperiment artexp(problem, alt, alt, results);
#endif
CCPLConsole cplc;
CRepeatThreads rts(79, 100000, &cplc);
rts.AddThread(artexp);
CPLog1D problemBis;
CResults resultsBis(problemBis.GetDimensions());
CRSPSA altBis(resultsBis);
CArtificialExperiment artexpBis(problemBis, altBis, altBis, resultsBis);
rts.AddThread(artexpBis);
rts.Start();
rts.WaitForTermination();
}
/* execute instructions on this CPU until icount expires */
static int hd6309_execute(int cycles) /* NS 970908 */
{
hd6309_ICount = cycles - hd6309.extra_cycles;
hd6309.extra_cycles = 0;
if (hd6309.int_state & (HD6309_CWAI | HD6309_SYNC))
{
CALL_MAME_DEBUG;
hd6309_ICount = 0;
}
else
{
do
{
pPPC = pPC;
CALL_MAME_DEBUG;
hd6309.ireg = ROP(PCD);
PC++;
#ifdef BIG_SWITCH
switch( hd6309.ireg )
{
case 0x00: neg_di(); break;
case 0x01: oim_di(); break;
case 0x02: aim_di(); break;
case 0x03: com_di(); break;
case 0x04: lsr_di(); break;
case 0x05: eim_di(); break;
case 0x06: ror_di(); break;
case 0x07: asr_di(); break;
case 0x08: asl_di(); break;
case 0x09: rol_di(); break;
case 0x0a: dec_di(); break;
case 0x0b: tim_di(); break;
case 0x0c: inc_di(); break;
case 0x0d: tst_di(); break;
case 0x0e: jmp_di(); break;
case 0x0f: clr_di(); break;
case 0x10: pref10(); break;
case 0x11: pref11(); break;
case 0x12: nop(); break;
case 0x13: sync(); break;
case 0x14: sexw(); break;
case 0x15: IIError(); break;
case 0x16: lbra(); break;
case 0x17: lbsr(); break;
case 0x18: IIError(); break;
case 0x19: daa(); break;
case 0x1a: orcc(); break;
case 0x1b: IIError(); break;
case 0x1c: andcc(); break;
case 0x1d: sex(); break;
case 0x1e: exg(); break;
case 0x1f: tfr(); break;
case 0x20: bra(); break;
case 0x21: brn(); break;
case 0x22: bhi(); break;
case 0x23: bls(); break;
case 0x24: bcc(); break;
case 0x25: bcs(); break;
case 0x26: bne(); break;
case 0x27: beq(); break;
case 0x28: bvc(); break;
case 0x29: bvs(); break;
case 0x2a: bpl(); break;
case 0x2b: bmi(); break;
case 0x2c: bge(); break;
case 0x2d: blt(); break;
case 0x2e: bgt(); break;
case 0x2f: ble(); break;
case 0x30: leax(); break;
case 0x31: leay(); break;
case 0x32: leas(); break;
case 0x33: leau(); break;
case 0x34: pshs(); break;
case 0x35: puls(); break;
case 0x36: pshu(); break;
case 0x37: pulu(); break;
case 0x38: IIError(); break;
case 0x39: rts(); break;
case 0x3a: abx(); break;
case 0x3b: rti(); break;
case 0x3c: cwai(); break;
case 0x3d: mul(); break;
case 0x3e: IIError(); break;
case 0x3f: swi(); break;
case 0x40: nega(); break;
case 0x41: IIError(); break;
case 0x42: IIError(); break;
case 0x43: coma(); break;
case 0x44: lsra(); break;
case 0x45: IIError(); break;
case 0x46: rora(); break;
case 0x47: asra(); break;
case 0x48: asla(); break;
case 0x49: rola(); break;
case 0x4a: deca(); break;
case 0x4b: IIError(); break;
case 0x4c: inca(); break;
case 0x4d: tsta(); break;
case 0x4e: IIError(); break;
case 0x4f: clra(); break;
case 0x50: negb(); break;
case 0x51: IIError(); break;
case 0x52: IIError(); break;
case 0x53: comb(); break;
case 0x54: lsrb(); break;
case 0x55: IIError(); break;
case 0x56: rorb(); break;
case 0x57: asrb(); break;
case 0x58: aslb(); break;
case 0x59: rolb(); break;
case 0x5a: decb(); break;
case 0x5b: IIError(); break;
case 0x5c: incb(); break;
case 0x5d: tstb(); break;
case 0x5e: IIError(); break;
case 0x5f: clrb(); break;
case 0x60: neg_ix(); break;
case 0x61: oim_ix(); break;
case 0x62: aim_ix(); break;
case 0x63: com_ix(); break;
case 0x64: lsr_ix(); break;
case 0x65: eim_ix(); break;
case 0x66: ror_ix(); break;
case 0x67: asr_ix(); break;
case 0x68: asl_ix(); break;
case 0x69: rol_ix(); break;
case 0x6a: dec_ix(); break;
case 0x6b: tim_ix(); break;
case 0x6c: inc_ix(); break;
case 0x6d: tst_ix(); break;
case 0x6e: jmp_ix(); break;
case 0x6f: clr_ix(); break;
case 0x70: neg_ex(); break;
case 0x71: oim_ex(); break;
case 0x72: aim_ex(); break;
case 0x73: com_ex(); break;
case 0x74: lsr_ex(); break;
case 0x75: eim_ex(); break;
case 0x76: ror_ex(); break;
case 0x77: asr_ex(); break;
case 0x78: asl_ex(); break;
case 0x79: rol_ex(); break;
case 0x7a: dec_ex(); break;
case 0x7b: tim_ex(); break;
case 0x7c: inc_ex(); break;
case 0x7d: tst_ex(); break;
case 0x7e: jmp_ex(); break;
case 0x7f: clr_ex(); break;
case 0x80: suba_im(); break;
case 0x81: cmpa_im(); break;
case 0x82: sbca_im(); break;
case 0x83: subd_im(); break;
case 0x84: anda_im(); break;
case 0x85: bita_im(); break;
case 0x86: lda_im(); break;
case 0x87: IIError(); break;
case 0x88: eora_im(); break;
case 0x89: adca_im(); break;
case 0x8a: ora_im(); break;
case 0x8b: adda_im(); break;
case 0x8c: cmpx_im(); break;
case 0x8d: bsr(); break;
case 0x8e: ldx_im(); break;
case 0x8f: IIError(); break;
case 0x90: suba_di(); break;
case 0x91: cmpa_di(); break;
case 0x92: sbca_di(); break;
case 0x93: subd_di(); break;
case 0x94: anda_di(); break;
case 0x95: bita_di(); break;
case 0x96: lda_di(); break;
case 0x97: sta_di(); break;
case 0x98: eora_di(); break;
case 0x99: adca_di(); break;
case 0x9a: ora_di(); break;
case 0x9b: adda_di(); break;
case 0x9c: cmpx_di(); break;
case 0x9d: jsr_di(); break;
case 0x9e: ldx_di(); break;
case 0x9f: stx_di(); break;
case 0xa0: suba_ix(); break;
case 0xa1: cmpa_ix(); break;
case 0xa2: sbca_ix(); break;
case 0xa3: subd_ix(); break;
case 0xa4: anda_ix(); break;
case 0xa5: bita_ix(); break;
case 0xa6: lda_ix(); break;
case 0xa7: sta_ix(); break;
case 0xa8: eora_ix(); break;
case 0xa9: adca_ix(); break;
case 0xaa: ora_ix(); break;
case 0xab: adda_ix(); break;
case 0xac: cmpx_ix(); break;
case 0xad: jsr_ix(); break;
case 0xae: ldx_ix(); break;
case 0xaf: stx_ix(); break;
case 0xb0: suba_ex(); break;
case 0xb1: cmpa_ex(); break;
case 0xb2: sbca_ex(); break;
case 0xb3: subd_ex(); break;
case 0xb4: anda_ex(); break;
case 0xb5: bita_ex(); break;
case 0xb6: lda_ex(); break;
case 0xb7: sta_ex(); break;
case 0xb8: eora_ex(); break;
case 0xb9: adca_ex(); break;
case 0xba: ora_ex(); break;
case 0xbb: adda_ex(); break;
case 0xbc: cmpx_ex(); break;
case 0xbd: jsr_ex(); break;
case 0xbe: ldx_ex(); break;
case 0xbf: stx_ex(); break;
case 0xc0: subb_im(); break;
case 0xc1: cmpb_im(); break;
case 0xc2: sbcb_im(); break;
case 0xc3: addd_im(); break;
case 0xc4: andb_im(); break;
case 0xc5: bitb_im(); break;
case 0xc6: ldb_im(); break;
case 0xc7: IIError(); break;
case 0xc8: eorb_im(); break;
case 0xc9: adcb_im(); break;
case 0xca: orb_im(); break;
case 0xcb: addb_im(); break;
case 0xcc: ldd_im(); break;
case 0xcd: ldq_im(); break; /* in m6809 was std_im */
case 0xce: ldu_im(); break;
case 0xcf: IIError(); break;
case 0xd0: subb_di(); break;
case 0xd1: cmpb_di(); break;
case 0xd2: sbcb_di(); break;
case 0xd3: addd_di(); break;
case 0xd4: andb_di(); break;
case 0xd5: bitb_di(); break;
case 0xd6: ldb_di(); break;
case 0xd7: stb_di(); break;
case 0xd8: eorb_di(); break;
case 0xd9: adcb_di(); break;
case 0xda: orb_di(); break;
case 0xdb: addb_di(); break;
case 0xdc: ldd_di(); break;
case 0xdd: std_di(); break;
case 0xde: ldu_di(); break;
case 0xdf: stu_di(); break;
case 0xe0: subb_ix(); break;
case 0xe1: cmpb_ix(); break;
case 0xe2: sbcb_ix(); break;
case 0xe3: addd_ix(); break;
case 0xe4: andb_ix(); break;
case 0xe5: bitb_ix(); break;
case 0xe6: ldb_ix(); break;
case 0xe7: stb_ix(); break;
case 0xe8: eorb_ix(); break;
case 0xe9: adcb_ix(); break;
case 0xea: orb_ix(); break;
case 0xeb: addb_ix(); break;
case 0xec: ldd_ix(); break;
case 0xed: std_ix(); break;
case 0xee: ldu_ix(); break;
case 0xef: stu_ix(); break;
case 0xf0: subb_ex(); break;
case 0xf1: cmpb_ex(); break;
case 0xf2: sbcb_ex(); break;
case 0xf3: addd_ex(); break;
case 0xf4: andb_ex(); break;
case 0xf5: bitb_ex(); break;
case 0xf6: ldb_ex(); break;
case 0xf7: stb_ex(); break;
case 0xf8: eorb_ex(); break;
case 0xf9: adcb_ex(); break;
case 0xfa: orb_ex(); break;
case 0xfb: addb_ex(); break;
case 0xfc: ldd_ex(); break;
case 0xfd: std_ex(); break;
case 0xfe: ldu_ex(); break;
case 0xff: stu_ex(); break;
}
#else
(*hd6309_main[hd6309.ireg])();
#endif /* BIG_SWITCH */
hd6309_ICount -= cycle_counts_page0[hd6309.ireg];
} while( hd6309_ICount > 0 );
hd6309_ICount -= hd6309.extra_cycles;
hd6309.extra_cycles = 0;
}
return cycles - hd6309_ICount; /* NS 970908 */
}
/**
* @brief emulate instruction
* @return returns false if something goes wrong (e.g. illegal instruction)
*
* Current limitations:
*
* - Illegal instructions are not implemented
* - Excess cycles due to page boundary crossing are not calculated
* - Some known architectural bugs are not emulated
*/
bool Cpu::emulate()
{
/* fetch instruction */
uint8_t insn = fetch_op();
bool retval = true;
/* emulate instruction */
switch(insn)
{
/* BRK */
case 0x0: brk(); break;
/* ORA (nn,X) */
case 0x1: ora(load_byte(addr_indx()),6); break;
/* ORA nn */
case 0x5: ora(load_byte(addr_zero()),3); break;
/* ASL nn */
case 0x6: asl_mem(addr_zero(),5); break;
/* PHP */
case 0x8: php(); break;
/* ORA #nn */
case 0x9: ora(fetch_op(),2); break;
/* ASL A */
case 0xA: asl_a(); break;
/* ORA nnnn */
case 0xD: ora(load_byte(addr_abs()),4); break;
/* ASL nnnn */
case 0xE: asl_mem(addr_abs(),6); break;
/* BPL nn */
case 0x10: bpl(); break;
/* ORA (nn,Y) */
case 0x11: ora(load_byte(addr_indy()),5); break;
/* ORA nn,X */
case 0x15: ora(load_byte(addr_zerox()),4); break;
/* ASL nn,X */
case 0x16: asl_mem(addr_zerox(),6); break;
/* CLC */
case 0x18: clc(); break;
/* ORA nnnn,Y */
case 0x19: ora(load_byte(addr_absy()),4); break;
/* ORA nnnn,X */
case 0x1D: ora(load_byte(addr_absx()),4); break;
/* ASL nnnn,X */
case 0x1E: asl_mem(addr_absx(),7); break;
/* JSR */
case 0x20: jsr(); break;
/* AND (nn,X) */
case 0x21: _and(load_byte(addr_indx()),6); break;
/* BIT nn */
case 0x24: bit(addr_zero(),3); break;
/* AND nn */
case 0x25: _and(load_byte(addr_zero()),3); break;
/* ROL nn */
case 0x26: rol_mem(addr_zero(),5); break;
/* PLP */
case 0x28: plp(); break;
/* AND #nn */
case 0x29: _and(fetch_op(),2); break;
/* ROL A */
case 0x2A: rol_a(); break;
/* BIT nnnn */
case 0x2C: bit(addr_abs(),4); break;
/* AND nnnn */
case 0x2D: _and(load_byte(addr_abs()),4); break;
/* ROL nnnn */
case 0x2E: rol_mem(addr_abs(),6); break;
/* BMI nn */
case 0x30: bmi(); break;
/* AND (nn,Y) */
case 0x31: _and(load_byte(addr_indy()),5); break;
/* AND nn,X */
case 0x35: _and(load_byte(addr_zerox()),4); break;
/* ROL nn,X */
case 0x36: rol_mem(addr_zerox(),6); break;
/* SEC */
case 0x38: sec(); break;
/* AND nnnn,Y */
case 0x39: _and(load_byte(addr_absy()),4); break;
/* AND nnnn,X */
case 0x3D: _and(load_byte(addr_absx()),4); break;
/* ROL nnnn,X */
case 0x3E: rol_mem(addr_absx(),7); break;
/* RTI */
case 0x40: rti(); break;
/* EOR (nn,X) */
case 0x41: eor(load_byte(addr_indx()),6); break;
/* EOR nn */
case 0x45: eor(load_byte(addr_zero()),3); break;
/* LSR nn */
case 0x46: lsr_mem(addr_zero(),5); break;
/* PHA */
case 0x48: pha(); break;
/* EOR #nn */
case 0x49: eor(fetch_op(),2); break;
/* BVC */
case 0x50: bvc(); break;
/* JMP nnnn */
case 0x4C: jmp(); break;
/* EOR nnnn */
case 0x4D: eor(load_byte(addr_abs()),4); break;
/* LSR A */
case 0x4A: lsr_a(); break;
/* LSR nnnn */
case 0x4E: lsr_mem(addr_abs(),6); break;
/* EOR (nn,Y) */
case 0x51: eor(load_byte(addr_indy()),5); break;
/* EOR nn,X */
case 0x55: eor(load_byte(addr_zerox()),4); break;
/* LSR nn,X */
case 0x56: lsr_mem(addr_zerox(),6); break;
/* CLI */
case 0x58: cli(); break;
/* EOR nnnn,Y */
case 0x59: eor(load_byte(addr_absy()),4); break;
/* EOR nnnn,X */
case 0x5D: eor(load_byte(addr_absx()),4); break;
/* LSR nnnn,X */
case 0x5E: lsr_mem(addr_absx(),7); break;
/* RTS */
case 0x60: rts(); break;
/* ADC (nn,X) */
case 0x61: adc(load_byte(addr_indx()),6); break;
/* ADC nn */
case 0x65: adc(load_byte(addr_zero()),3); break;
/* ROR nn */
case 0x66: ror_mem(addr_zero(),5); break;
/* PLA */
case 0x68: pla(); break;
/* ADC #nn */
case 0x69: adc(fetch_op(),2); break;
/* ROR A */
case 0x6A: ror_a(); break;
/* JMP (nnnn) */
case 0x6C: jmp_ind(); break;
/* ADC nnnn */
case 0x6D: adc(load_byte(addr_abs()),4); break;
/* ROR nnnn */
case 0x6E: ror_mem(addr_abs(),6); break;
/* BVS */
case 0x70: bvs(); break;
/* ADC (nn,Y) */
case 0x71: adc(load_byte(addr_indy()),5); break;
/* ADC nn,X */
case 0x75: adc(load_byte(addr_zerox()),4); break;
/* ROR nn,X */
case 0x76: ror_mem(addr_zerox(),6); break;
/* SEI */
case 0x78: sei(); break;
/* ADC nnnn,Y */
case 0x79: adc(load_byte(addr_absy()),4); break;
/* ADC nnnn,X */
case 0x7D: adc(load_byte(addr_absx()),4); break;
/* ROR nnnn,X */
case 0x7E: ror_mem(addr_absx(),7); break;
/* STA (nn,X) */
case 0x81: sta(addr_indx(),6); break;
/* STY nn */
case 0x84: sty(addr_zero(),3); break;
/* STA nn */
case 0x85: sta(addr_zero(),3); break;
/* STX nn */
case 0x86: stx(addr_zero(),3); break;
/* DEY */
case 0x88: dey(); break;
/* TXA */
case 0x8A: txa(); break;
/* STY nnnn */
case 0x8C: sty(addr_abs(),4); break;
/* STA nnnn */
case 0x8D: sta(addr_abs(),4); break;
/* STX nnnn */
case 0x8E: stx(addr_abs(),4); break;
/* BCC nn */
case 0x90: bcc(); break;
/* STA (nn,Y) */
case 0x91: sta(addr_indy(),6); break;
/* STY nn,X */
case 0x94: sty(addr_zerox(),4); break;
/* STA nn,X */
case 0x95: sta(addr_zerox(),4); break;
/* STX nn,Y */
case 0x96: stx(addr_zeroy(),4); break;
/* TYA */
case 0x98: tya(); break;
/* STA nnnn,Y */
case 0x99: sta(addr_absy(),5); break;
/* TXS */
case 0x9A: txs(); break;
/* STA nnnn,X */
case 0x9D: sta(addr_absx(),5); break;
/* LDY #nn */
case 0xA0: ldy(fetch_op(),2); break;
/* LDA (nn,X) */
case 0xA1: lda(load_byte(addr_indx()),6); break;
/* LDX #nn */
case 0xA2: ldx(fetch_op(),2); break;
/* LDY nn */
case 0xA4: ldy(load_byte(addr_zero()),3); break;
/* LDA nn */
case 0xA5: lda(load_byte(addr_zero()),3); break;
/* LDX nn */
case 0xA6: ldx(load_byte(addr_zero()),3); break;
/* TAY */
case 0xA8: tay(); break;
/* LDA #nn */
case 0xA9: lda(fetch_op(),2); break;
/* TAX */
case 0xAA: tax(); break;
/* LDY nnnn */
case 0xAC: ldy(load_byte(addr_abs()),4); break;
/* LDA nnnn */
case 0xAD: lda(load_byte(addr_abs()),4); break;
/* LDX nnnn */
case 0xAE: ldx(load_byte(addr_abs()),4); break;
/* BCS nn */
case 0xB0: bcs(); break;
/* LDA (nn,Y) */
case 0xB1: lda(load_byte(addr_indy()),5); break;
/* LDY nn,X */
case 0xB4: ldy(load_byte(addr_zerox()),3); break;
/* LDA nn,X */
case 0xB5: lda(load_byte(addr_zerox()),3); break;
/* LDX nn,Y */
case 0xB6: ldx(load_byte(addr_zeroy()),3); break;
/* CLV */
case 0xB8: clv(); break;
/* LDA nnnn,Y */
case 0xB9: lda(load_byte(addr_absy()),4); break;
/* TSX */
case 0xBA: tsx(); break;
/* LDY nnnn,X */
case 0xBC: ldy(load_byte(addr_absx()),4); break;
/* LDA nnnn,X */
case 0xBD: lda(load_byte(addr_absx()),4); break;
/* LDX nnnn,Y */
case 0xBE: ldx(load_byte(addr_absy()),4); break;
/* CPY #nn */
case 0xC0: cpy(fetch_op(),2); break;
/* CMP (nn,X) */
case 0xC1: cmp(load_byte(addr_indx()),6); break;
/* CPY nn */
case 0xC4: cpy(load_byte(addr_zero()),3); break;
/* CMP nn */
case 0xC5: cmp(load_byte(addr_zero()),3); break;
/* DEC nn */
case 0xC6: dec(addr_zero(),5); break;
/* INY */
case 0xC8: iny(); break;
/* CMP #nn */
case 0xC9: cmp(fetch_op(),2); break;
/* DEX */
case 0xCA: dex(); break;
/* CPY nnnn */
case 0xCC: cpy(load_byte(addr_abs()),4); break;
/* CMP nnnn */
case 0xCD: cmp(load_byte(addr_abs()),4); break;
/* DEC nnnn */
case 0xCE: dec(addr_abs(),6); break;
/* BNE nn */
case 0xD0: bne(); break;
/* CMP (nn,Y) */
case 0xD1: cmp(load_byte(addr_indy()),5); break;
/* CMP nn,X */
case 0xD5: cmp(load_byte(addr_zerox()),4); break;
/* DEC nn,X */
case 0xD6: dec(addr_zerox(),6); break;
/* CLD */
case 0xD8: cld(); break;
/* CMP nnnn,Y */
case 0xD9: cmp(load_byte(addr_absy()),4); break;
/* CMP nnnn,X */
case 0xDD: cmp(load_byte(addr_absx()),4); break;
/* DEC nnnn,X */
case 0xDE: dec(addr_absx(),7); break;
/* CPX #nn */
case 0xE0: cpx(fetch_op(),2); break;
/* SBC (nn,X) */
case 0xE1: sbc(load_byte(addr_indx()),6); break;
/* CPX nn */
case 0xE4: cpx(load_byte(addr_zero()),3); break;
/* SBC nn */
case 0xE5: sbc(load_byte(addr_zero()),3); break;
/* INC nn */
case 0xE6: inc(addr_zero(),5); break;
/* INX */
case 0xE8: inx(); break;
/* SBC #nn */
case 0xE9: sbc(fetch_op(),2); break;
/* NOP */
case 0xEA: nop(); break;
/* CPX nnnn */
case 0xEC: cpx(load_byte(addr_abs()),4); break;
/* SBC nnnn */
case 0xED: sbc(load_byte(addr_abs()),4); break;
/* INC nnnn */
case 0xEE: inc(addr_abs(),6); break;
/* BEQ nn */
case 0xF0: beq(); break;
/* SBC (nn,Y) */
case 0xF1: sbc(load_byte(addr_indy()),5); break;
/* SBC nn,X */
case 0xF5: sbc(load_byte(addr_zerox()),4); break;
/* INC nn,X */
case 0xF6: inc(addr_zerox(),6); break;
/* SED */
case 0xF8: sed(); break;
/* SBC nnnn,Y */
case 0xF9: sbc(load_byte(addr_absy()),4); break;
/* SBC nnnn,X */
case 0xFD: sbc(load_byte(addr_absx()),4); break;
/* INC nnnn,X */
case 0xFE: inc(addr_absx(),7); break;
/* Unknown or illegal instruction */
default:
D("Unknown instruction: %X at %04x\n", insn,pc());
retval = false;
}
return retval;
}
/* execute instructions on this CPU until icount expires */
void m6805_base_device::execute_run()
{
UINT8 ireg;
S = SP_ADJUST( S ); /* Taken from CPU_SET_CONTEXT when pointer'afying */
do
{
if (m_pending_interrupts != 0)
{
interrupt();
}
debugger_instruction_hook(this, PC);
ireg=M_RDOP(PC++);
switch( ireg )
{
case 0x00: brset(0x01); break;
case 0x01: brclr(0x01); break;
case 0x02: brset(0x02); break;
case 0x03: brclr(0x02); break;
case 0x04: brset(0x04); break;
case 0x05: brclr(0x04); break;
case 0x06: brset(0x08); break;
case 0x07: brclr(0x08); break;
case 0x08: brset(0x10); break;
case 0x09: brclr(0x10); break;
case 0x0A: brset(0x20); break;
case 0x0B: brclr(0x20); break;
case 0x0C: brset(0x40); break;
case 0x0D: brclr(0x40); break;
case 0x0E: brset(0x80); break;
case 0x0F: brclr(0x80); break;
case 0x10: bset(0x01); break;
case 0x11: bclr(0x01); break;
case 0x12: bset(0x02); break;
case 0x13: bclr(0x02); break;
case 0x14: bset(0x04); break;
case 0x15: bclr(0x04); break;
case 0x16: bset(0x08); break;
case 0x17: bclr(0x08); break;
case 0x18: bset(0x10); break;
case 0x19: bclr(0x10); break;
case 0x1a: bset(0x20); break;
case 0x1b: bclr(0x20); break;
case 0x1c: bset(0x40); break;
case 0x1d: bclr(0x40); break;
case 0x1e: bset(0x80); break;
case 0x1f: bclr(0x80); break;
case 0x20: bra(); break;
case 0x21: brn(); break;
case 0x22: bhi(); break;
case 0x23: bls(); break;
case 0x24: bcc(); break;
case 0x25: bcs(); break;
case 0x26: bne(); break;
case 0x27: beq(); break;
case 0x28: bhcc(); break;
case 0x29: bhcs(); break;
case 0x2a: bpl(); break;
case 0x2b: bmi(); break;
case 0x2c: bmc(); break;
case 0x2d: bms(); break;
case 0x2e: bil(); break;
case 0x2f: bih(); break;
case 0x30: neg_di(); break;
case 0x31: illegal(); break;
case 0x32: illegal(); break;
case 0x33: com_di(); break;
case 0x34: lsr_di(); break;
case 0x35: illegal(); break;
case 0x36: ror_di(); break;
case 0x37: asr_di(); break;
case 0x38: lsl_di(); break;
case 0x39: rol_di(); break;
case 0x3a: dec_di(); break;
case 0x3b: illegal(); break;
case 0x3c: inc_di(); break;
case 0x3d: tst_di(); break;
case 0x3e: illegal(); break;
case 0x3f: clr_di(); break;
case 0x40: nega(); break;
case 0x41: illegal(); break;
case 0x42: illegal(); break;
case 0x43: coma(); break;
case 0x44: lsra(); break;
case 0x45: illegal(); break;
case 0x46: rora(); break;
case 0x47: asra(); break;
case 0x48: lsla(); break;
case 0x49: rola(); break;
case 0x4a: deca(); break;
case 0x4b: illegal(); break;
case 0x4c: inca(); break;
case 0x4d: tsta(); break;
case 0x4e: illegal(); break;
case 0x4f: clra(); break;
case 0x50: negx(); break;
case 0x51: illegal(); break;
case 0x52: illegal(); break;
case 0x53: comx(); break;
case 0x54: lsrx(); break;
case 0x55: illegal(); break;
case 0x56: rorx(); break;
case 0x57: asrx(); break;
case 0x58: aslx(); break;
case 0x59: rolx(); break;
case 0x5a: decx(); break;
case 0x5b: illegal(); break;
case 0x5c: incx(); break;
case 0x5d: tstx(); break;
case 0x5e: illegal(); break;
case 0x5f: clrx(); break;
case 0x60: neg_ix1(); break;
case 0x61: illegal(); break;
case 0x62: illegal(); break;
case 0x63: com_ix1(); break;
case 0x64: lsr_ix1(); break;
case 0x65: illegal(); break;
case 0x66: ror_ix1(); break;
case 0x67: asr_ix1(); break;
case 0x68: lsl_ix1(); break;
case 0x69: rol_ix1(); break;
case 0x6a: dec_ix1(); break;
case 0x6b: illegal(); break;
case 0x6c: inc_ix1(); break;
case 0x6d: tst_ix1(); break;
case 0x6e: illegal(); break;
case 0x6f: clr_ix1(); break;
case 0x70: neg_ix(); break;
case 0x71: illegal(); break;
case 0x72: illegal(); break;
case 0x73: com_ix(); break;
case 0x74: lsr_ix(); break;
case 0x75: illegal(); break;
case 0x76: ror_ix(); break;
case 0x77: asr_ix(); break;
case 0x78: lsl_ix(); break;
case 0x79: rol_ix(); break;
case 0x7a: dec_ix(); break;
case 0x7b: illegal(); break;
case 0x7c: inc_ix(); break;
case 0x7d: tst_ix(); break;
case 0x7e: illegal(); break;
case 0x7f: clr_ix(); break;
case 0x80: rti(); break;
case 0x81: rts(); break;
case 0x82: illegal(); break;
case 0x83: swi(); break;
case 0x84: illegal(); break;
case 0x85: illegal(); break;
case 0x86: illegal(); break;
case 0x87: illegal(); break;
case 0x88: illegal(); break;
case 0x89: illegal(); break;
case 0x8a: illegal(); break;
case 0x8b: illegal(); break;
case 0x8c: illegal(); break;
case 0x8d: illegal(); break;
case 0x8e: illegal(); break;
case 0x8f: illegal(); break;
case 0x90: illegal(); break;
case 0x91: illegal(); break;
case 0x92: illegal(); break;
case 0x93: illegal(); break;
case 0x94: illegal(); break;
case 0x95: illegal(); break;
case 0x96: illegal(); break;
case 0x97: tax(); break;
case 0x98: CLC; break;
case 0x99: SEC; break;
#if IRQ_LEVEL_DETECT
case 0x9a: CLI; if (m_irq_state != CLEAR_LINE) m_pending_interrupts |= 1 << M6805_IRQ_LINE; break;
#else
case 0x9a: CLI; break;
#endif
case 0x9b: SEI; break;
case 0x9c: rsp(); break;
case 0x9d: nop(); break;
case 0x9e: illegal(); break;
case 0x9f: txa(); break;
case 0xa0: suba_im(); break;
case 0xa1: cmpa_im(); break;
case 0xa2: sbca_im(); break;
case 0xa3: cpx_im(); break;
case 0xa4: anda_im(); break;
case 0xa5: bita_im(); break;
case 0xa6: lda_im(); break;
case 0xa7: illegal(); break;
case 0xa8: eora_im(); break;
case 0xa9: adca_im(); break;
case 0xaa: ora_im(); break;
case 0xab: adda_im(); break;
case 0xac: illegal(); break;
case 0xad: bsr(); break;
case 0xae: ldx_im(); break;
case 0xaf: illegal(); break;
case 0xb0: suba_di(); break;
case 0xb1: cmpa_di(); break;
case 0xb2: sbca_di(); break;
case 0xb3: cpx_di(); break;
case 0xb4: anda_di(); break;
case 0xb5: bita_di(); break;
case 0xb6: lda_di(); break;
case 0xb7: sta_di(); break;
case 0xb8: eora_di(); break;
case 0xb9: adca_di(); break;
case 0xba: ora_di(); break;
case 0xbb: adda_di(); break;
case 0xbc: jmp_di(); break;
case 0xbd: jsr_di(); break;
case 0xbe: ldx_di(); break;
case 0xbf: stx_di(); break;
case 0xc0: suba_ex(); break;
case 0xc1: cmpa_ex(); break;
case 0xc2: sbca_ex(); break;
case 0xc3: cpx_ex(); break;
case 0xc4: anda_ex(); break;
case 0xc5: bita_ex(); break;
case 0xc6: lda_ex(); break;
case 0xc7: sta_ex(); break;
case 0xc8: eora_ex(); break;
case 0xc9: adca_ex(); break;
case 0xca: ora_ex(); break;
case 0xcb: adda_ex(); break;
case 0xcc: jmp_ex(); break;
case 0xcd: jsr_ex(); break;
case 0xce: ldx_ex(); break;
case 0xcf: stx_ex(); break;
case 0xd0: suba_ix2(); break;
case 0xd1: cmpa_ix2(); break;
case 0xd2: sbca_ix2(); break;
case 0xd3: cpx_ix2(); break;
case 0xd4: anda_ix2(); break;
case 0xd5: bita_ix2(); break;
case 0xd6: lda_ix2(); break;
case 0xd7: sta_ix2(); break;
case 0xd8: eora_ix2(); break;
case 0xd9: adca_ix2(); break;
case 0xda: ora_ix2(); break;
case 0xdb: adda_ix2(); break;
case 0xdc: jmp_ix2(); break;
case 0xdd: jsr_ix2(); break;
case 0xde: ldx_ix2(); break;
case 0xdf: stx_ix2(); break;
case 0xe0: suba_ix1(); break;
case 0xe1: cmpa_ix1(); break;
case 0xe2: sbca_ix1(); break;
case 0xe3: cpx_ix1(); break;
case 0xe4: anda_ix1(); break;
case 0xe5: bita_ix1(); break;
case 0xe6: lda_ix1(); break;
case 0xe7: sta_ix1(); break;
case 0xe8: eora_ix1(); break;
case 0xe9: adca_ix1(); break;
case 0xea: ora_ix1(); break;
case 0xeb: adda_ix1(); break;
case 0xec: jmp_ix1(); break;
case 0xed: jsr_ix1(); break;
case 0xee: ldx_ix1(); break;
case 0xef: stx_ix1(); break;
case 0xf0: suba_ix(); break;
case 0xf1: cmpa_ix(); break;
case 0xf2: sbca_ix(); break;
case 0xf3: cpx_ix(); break;
case 0xf4: anda_ix(); break;
case 0xf5: bita_ix(); break;
case 0xf6: lda_ix(); break;
case 0xf7: sta_ix(); break;
case 0xf8: eora_ix(); break;
case 0xf9: adca_ix(); break;
case 0xfa: ora_ix(); break;
case 0xfb: adda_ix(); break;
case 0xfc: jmp_ix(); break;
case 0xfd: jsr_ix(); break;
case 0xfe: ldx_ix(); break;
case 0xff: stx_ix(); break;
}
m_icount -= m_cycles1[ireg];
} while( m_icount > 0 );
}
void DrvOpen(void)
{
char * f=nil;
char *name;
struct DRV *p, *drv=Drivers;
void *priv;
int err,found=0;
#if 0 /* need a different test here */
if((long)((Ptr)gPC-(Ptr)theROM)-2 != 0x14002l)
{
exception=4;
extraFlag=true;
nInst2=nInst;
nInst=0;
return;
}
#endif
name=(char *)((Ptr)theROM+((*aReg)&ADDR_MASK_E));
//printf("DrvOpen: %s\n",name+2);
#if 0
if(*aReg>=RTOP || ((*aReg+RW(name))>=RTOP))
{
*reg=-18; /* overflow */
goto end;
}
#endif
/* get device */
p=dget_drv();
found=(*(p->open_test))(p-Drivers,name);
if (!found)
{
reg[0]=QERR_NF;
goto end;
}
if (found==-2)
{
reg[0]=qerrno;
goto end;
}
if (found==-1)
{
reg[0]=QERR_BN;
goto end;
}
err=(*(p->open))(p-Drivers,&priv);
if (err==0)
{
reg[1]=DRV_SIZE;
reg[2]=0;
QLvector(0xc0,20000l);
if ((uw16)reg[0]) goto end;
f=a0addr(false);
if (f)
{
DSET_ID(f,DRV_ID);
DSET_PRIV(f,priv);
}
}
if (err>=0)
reg[0]=0;
if (err<0)
reg[0]=err;
end:
rts();
}
/* Pi SIO External/Status interrupts (for the B channel)
* This can be caused by a receiver abort, or a Tx UNDERRUN/EOM.
* Receiver automatically goes to Hunt on an abort.
*
* If the Tx Underrun interrupt hits, change state and
* issue a reset command for it, and return.
*/
static void b_exint(struct pi_local *lp)
{
unsigned long flags;
char st;
int cmd;
char c;
cmd = CTL + lp->base;
save_flags(flags);
cli(); /* disable interrupts */
st = rdscc(lp->cardbase, cmd, R0); /* Fetch status */
/* reset external status latch */
wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
switch (lp->tstate) {
case ACTIVE: /* Unexpected underrun */
free_p(lp->sndbuf);
lp->sndbuf = NULL;
wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
lp->tstate = FLAGOUT;
lp->stats.tx_errors++;
lp->stats.tx_fifo_errors++;
tdelay(lp, lp->squeldelay);
restore_flags(flags);
return;
case UNDERRUN:
lp->tstate = CRCOUT;
restore_flags(flags);
return;
case FLAGOUT:
/* Find a frame for transmission */
if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
/* Nothing to send - return to receive mode
* Tx OFF now - flag should have gone
*/
rts(lp, OFF);
lp->tstate = IDLE;
restore_flags(flags);
return;
}
lp->txptr = lp->sndbuf->data;
lp->txptr++; /* Ignore KISS control byte */
lp->txcnt = (int) lp->sndbuf->len - 1;
/* Get first char to send */
lp->txcnt--;
c = *lp->txptr++;
wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC); /* reset for next frame */
/* Send abort on underrun */
if (lp->speed) { /* If internally clocked */
wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
} else {
wrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
}
wrtscc(lp->cardbase, cmd, R8, c); /* First char out now */
wrtscc(lp->cardbase, cmd, R0, RES_EOM_L); /* Reset end of message latch */
#ifdef STUFF2
/* stuff an extra one if we can */
if (lp->txcnt) {
lp->txcnt--;
c = *lp->txptr++;
/* Wait for tx buffer empty */
while((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
;
wrtscc(lp->cardbase, cmd, R8, c);
}
#endif
/* select transmit interrupts to enable */
wrtscc(lp->cardbase, cmd, R15, TxUIE); /* allow Underrun int only */
wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
wrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB); /* Tx/Ext ints */
lp->tstate = ACTIVE; /* char going out now */
restore_flags(flags);
return;
case DEFER:
/* Check DCD - debounce it
* See Intel Microcommunications Handbook, p2-308
*/
wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
lp->tstate = DEFER;
tdelay(lp, 100);
/* defer until DCD transition or timeout */
wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
restore_flags(flags);
return;
}
if (random() > lp->persist) {
lp->tstate = DEFER;
tdelay(lp, lp->slotime);
restore_flags(flags);
return;
}
rts(lp, ON); /* Transmitter on */
lp->tstate = ST_TXDELAY;
tdelay(lp, lp->txdelay);
restore_flags(flags);
return;
case ST_TXDELAY:
/* Get first char to send */
lp->txcnt--;
c = *lp->txptr++;
wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC); /* reset for next frame */
/* Send abort on underrun */
if (lp->speed) { /* If internally clocked */
wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
} else {
wrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
}
wrtscc(lp->cardbase, cmd, R8, c); /* First char out now */
wrtscc(lp->cardbase, cmd, R0, RES_EOM_L); /* Reset end of message latch */
#ifdef STUFF2
/* stuff an extra one if we can */
if (lp->txcnt) {
lp->txcnt--;
c = *lp->txptr++;
/* Wait for tx buffer empty */
while((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
;
wrtscc(lp->cardbase, cmd, R8, c);
}
#endif
/* select transmit interrupts to enable */
wrtscc(lp->cardbase, cmd, R15, TxUIE); /* allow Underrun int only */
wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
/* Tx/Extern ints on */
wrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);
lp->tstate = ACTIVE; /* char going out now */
restore_flags(flags);
return;
}
/* Receive Mode only
* This triggers when hunt mode is entered, & since an ABORT
* automatically enters hunt mode, we use that to clean up
* any waiting garbage
*/
if ((lp->rstate == ACTIVE) && (st & BRK_ABRT)) {
(void) rdscc(lp->cardbase, cmd, R8);
(void) rdscc(lp->cardbase, cmd, R8);
(void) rdscc(lp->cardbase, cmd, R8);
lp->rcp = lp->rcvbuf->data;
lp->rcvbuf->cnt = 0; /* rewind on DCD transition */
}
restore_flags(flags);
}
static void b_txint(struct pi_local *lp)
{
unsigned long flags;
int cmd;
unsigned char c;
save_flags(flags);
cli();
cmd = CTL + lp->base;
switch (lp->tstate) {
case CRCOUT:
lp->tstate = FLAGOUT;
tdelay(lp, lp->squeldelay);
restore_flags(flags);
return;
case IDLE:
/* Transmitter idle. Find a frame for transmission */
if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
/* Nothing to send - return to receive mode
* Tx OFF now - flag should have gone
*/
rts(lp, OFF);
restore_flags(flags);
return;
}
lp->txptr = lp->sndbuf->data;
lp->txptr++; /* Ignore KISS control byte */
lp->txcnt = (int) lp->sndbuf->len - 1;
/* If a buffer to send, we drop thru here */
case DEFER: /* we may have deferred prev xmit attempt */
/* Check DCD - debounce it */
/* See Intel Microcommunications Handbook, p2-308 */
wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
lp->tstate = DEFER;
tdelay(lp, 100);
/* defer until DCD transition or timeout */
wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
restore_flags(flags);
return;
}
if (random() > lp->persist) {
lp->tstate = DEFER;
tdelay(lp, lp->slotime);
restore_flags(flags);
return;
}
rts(lp, ON); /* Transmitter on */
lp->tstate = ST_TXDELAY;
tdelay(lp, lp->txdelay);
restore_flags(flags);
return;
case ACTIVE:
/* Here we are actively sending a frame */
if (lp->txcnt--) {
c = *lp->txptr++;
/* next char is gone */
wrtscc(lp->cardbase, cmd, R8, c);
/* stuffing a char satisfies Interrupt condition */
} else {
/* No more to send */
free_p(lp->sndbuf);
lp->sndbuf = NULL;
if ((rdscc(lp->cardbase, cmd, R0) & 0x40)) {
/* Did we underrun? */
/* unexpected underrun */
lp->stats.tx_errors++;
lp->stats.tx_fifo_errors++;
wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
lp->tstate = FLAGOUT;
tdelay(lp, lp->squeldelay);
restore_flags(flags);
return;
}
lp->tstate = UNDERRUN; /* Now we expect to underrun */
/* Send flags on underrun */
if (lp->speed) { /* If internally clocked */
wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
} else {
wrtscc(lp->cardbase, cmd, R10, CRCPS);
}
wrtscc(lp->cardbase, cmd, R0, RES_Tx_P); /* reset Tx Int Pend */
}
restore_flags(flags);
return; /* back to wait for interrupt */
} /* end switch */
restore_flags(flags);
}
static void a_exint(struct pi_local *lp)
{
unsigned long flags;
int cmd;
char st;
int length;
save_flags(flags);
cli(); /* disable interrupts */
st = rdscc(lp->cardbase, lp->base + CTL, R0); /* Fetch status */
/* reset external status latch */
wrtscc(lp->cardbase, CTL + lp->base, R0, RES_EXT_INT);
cmd = lp->base + CTL;
if ((lp->rstate >= ACTIVE) && (st & BRK_ABRT)) {
setup_rx_dma(lp);
lp->rstate = ACTIVE;
}
switch (lp->tstate) {
case ACTIVE:
free_p(lp->sndbuf);
lp->sndbuf = NULL;
lp->tstate = FLAGOUT;
tdelay(lp, lp->squeldelay);
break;
case FLAGOUT:
if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
/* Nothing to send - return to receive mode */
lp->tstate = IDLE;
rts(lp, OFF);
restore_flags(flags);
return;
}
/* NOTE - fall through if more to send */
case ST_TXDELAY:
/* Disable DMA chan */
disable_dma(lp->dmachan);
/* Set up for TX dma */
wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
/* Get all chars */
/* Strip KISS control byte */
length = lp->sndbuf->len - 1;
memcpy(lp->txdmabuf, &lp->sndbuf->data[1], length);
/* Setup DMA controller for tx */
setup_tx_dma(lp, length);
/* select transmit interrupts to enable */
/* Allow DMA on chan */
enable_dma(lp->dmachan);
/* reset CRC, Txint pend*/
wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC | RES_Tx_P);
/* allow Underrun int only */
wrtscc(lp->cardbase, cmd, R15, TxUIE);
/* Enable TX DMA */
wrtscc(lp->cardbase, cmd, R1, WT_RDY_ENAB | WT_FN_RDYFN | EXT_INT_ENAB);
/* Send CRC on underrun */
wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);
/* packet going out now */
lp->tstate = ACTIVE;
break;
case DEFER:
/* we have deferred prev xmit attempt
* See Intel Microcommunications Handbook, p2-308
*/
wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
lp->tstate = DEFER;
tdelay(lp, 100);
/* Defer until dcd transition or 100mS timeout */
wrtscc(lp->cardbase, CTL + lp->base, R15, CTSIE | DCDIE);
restore_flags(flags);
return;
}
if (random() > lp->persist) {
lp->tstate = DEFER;
tdelay(lp, lp->slotime);
restore_flags(flags);
return;
}
/* Assert RTS early minimize collision window */
wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
rts(lp, ON); /* Transmitter on */
lp->tstate = ST_TXDELAY;
tdelay(lp, lp->txdelay);
restore_flags(flags);
return;
} /* switch(lp->tstate) */
restore_flags(flags);
} /* a_exint() */
/* execute instructions on this CPU until icount expires */
static CPU_EXECUTE( m6809 ) /* NS 970908 */
{
m68_state_t *m68_state = get_safe_token(device);
m68_state->icount = cycles - m68_state->extra_cycles;
m68_state->extra_cycles = 0;
check_irq_lines(m68_state);
if (m68_state->int_state & (M6809_CWAI | M6809_SYNC))
{
debugger_instruction_hook(device, PCD);
m68_state->icount = 0;
}
else
{
do
{
pPPC = pPC;
debugger_instruction_hook(device, PCD);
m68_state->ireg = ROP(PCD);
PC++;
#if BIG_SWITCH
switch( m68_state->ireg )
{
case 0x00: neg_di(m68_state); break;
case 0x01: neg_di(m68_state); break; /* undocumented */
case 0x02: IIError(m68_state); break;
case 0x03: com_di(m68_state); break;
case 0x04: lsr_di(m68_state); break;
case 0x05: IIError(m68_state); break;
case 0x06: ror_di(m68_state); break;
case 0x07: asr_di(m68_state); break;
case 0x08: asl_di(m68_state); break;
case 0x09: rol_di(m68_state); break;
case 0x0a: dec_di(m68_state); break;
case 0x0b: IIError(m68_state); break;
case 0x0c: inc_di(m68_state); break;
case 0x0d: tst_di(m68_state); break;
case 0x0e: jmp_di(m68_state); break;
case 0x0f: clr_di(m68_state); break;
case 0x10: pref10(m68_state); break;
case 0x11: pref11(m68_state); break;
case 0x12: nop(m68_state); break;
case 0x13: sync(m68_state); break;
case 0x14: IIError(m68_state); break;
case 0x15: IIError(m68_state); break;
case 0x16: lbra(m68_state); break;
case 0x17: lbsr(m68_state); break;
case 0x18: IIError(m68_state); break;
case 0x19: daa(m68_state); break;
case 0x1a: orcc(m68_state); break;
case 0x1b: IIError(m68_state); break;
case 0x1c: andcc(m68_state); break;
case 0x1d: sex(m68_state); break;
case 0x1e: exg(m68_state); break;
case 0x1f: tfr(m68_state); break;
case 0x20: bra(m68_state); break;
case 0x21: brn(m68_state); break;
case 0x22: bhi(m68_state); break;
case 0x23: bls(m68_state); break;
case 0x24: bcc(m68_state); break;
case 0x25: bcs(m68_state); break;
case 0x26: bne(m68_state); break;
case 0x27: beq(m68_state); break;
case 0x28: bvc(m68_state); break;
case 0x29: bvs(m68_state); break;
case 0x2a: bpl(m68_state); break;
case 0x2b: bmi(m68_state); break;
case 0x2c: bge(m68_state); break;
case 0x2d: blt(m68_state); break;
case 0x2e: bgt(m68_state); break;
case 0x2f: ble(m68_state); break;
case 0x30: leax(m68_state); break;
case 0x31: leay(m68_state); break;
case 0x32: leas(m68_state); break;
case 0x33: leau(m68_state); break;
case 0x34: pshs(m68_state); break;
case 0x35: puls(m68_state); break;
case 0x36: pshu(m68_state); break;
case 0x37: pulu(m68_state); break;
case 0x38: IIError(m68_state); break;
case 0x39: rts(m68_state); break;
case 0x3a: abx(m68_state); break;
case 0x3b: rti(m68_state); break;
case 0x3c: cwai(m68_state); break;
case 0x3d: mul(m68_state); break;
case 0x3e: IIError(m68_state); break;
case 0x3f: swi(m68_state); break;
case 0x40: nega(m68_state); break;
case 0x41: IIError(m68_state); break;
case 0x42: IIError(m68_state); break;
case 0x43: coma(m68_state); break;
case 0x44: lsra(m68_state); break;
case 0x45: IIError(m68_state); break;
case 0x46: rora(m68_state); break;
case 0x47: asra(m68_state); break;
case 0x48: asla(m68_state); break;
case 0x49: rola(m68_state); break;
case 0x4a: deca(m68_state); break;
case 0x4b: IIError(m68_state); break;
case 0x4c: inca(m68_state); break;
case 0x4d: tsta(m68_state); break;
case 0x4e: IIError(m68_state); break;
case 0x4f: clra(m68_state); break;
case 0x50: negb(m68_state); break;
case 0x51: IIError(m68_state); break;
case 0x52: IIError(m68_state); break;
case 0x53: comb(m68_state); break;
case 0x54: lsrb(m68_state); break;
case 0x55: IIError(m68_state); break;
case 0x56: rorb(m68_state); break;
case 0x57: asrb(m68_state); break;
case 0x58: aslb(m68_state); break;
case 0x59: rolb(m68_state); break;
case 0x5a: decb(m68_state); break;
case 0x5b: IIError(m68_state); break;
case 0x5c: incb(m68_state); break;
case 0x5d: tstb(m68_state); break;
case 0x5e: IIError(m68_state); break;
case 0x5f: clrb(m68_state); break;
case 0x60: neg_ix(m68_state); break;
case 0x61: IIError(m68_state); break;
case 0x62: IIError(m68_state); break;
case 0x63: com_ix(m68_state); break;
case 0x64: lsr_ix(m68_state); break;
case 0x65: IIError(m68_state); break;
case 0x66: ror_ix(m68_state); break;
case 0x67: asr_ix(m68_state); break;
case 0x68: asl_ix(m68_state); break;
case 0x69: rol_ix(m68_state); break;
case 0x6a: dec_ix(m68_state); break;
case 0x6b: IIError(m68_state); break;
case 0x6c: inc_ix(m68_state); break;
case 0x6d: tst_ix(m68_state); break;
case 0x6e: jmp_ix(m68_state); break;
case 0x6f: clr_ix(m68_state); break;
case 0x70: neg_ex(m68_state); break;
case 0x71: IIError(m68_state); break;
case 0x72: IIError(m68_state); break;
case 0x73: com_ex(m68_state); break;
case 0x74: lsr_ex(m68_state); break;
case 0x75: IIError(m68_state); break;
case 0x76: ror_ex(m68_state); break;
case 0x77: asr_ex(m68_state); break;
case 0x78: asl_ex(m68_state); break;
case 0x79: rol_ex(m68_state); break;
case 0x7a: dec_ex(m68_state); break;
case 0x7b: IIError(m68_state); break;
case 0x7c: inc_ex(m68_state); break;
case 0x7d: tst_ex(m68_state); break;
case 0x7e: jmp_ex(m68_state); break;
case 0x7f: clr_ex(m68_state); break;
case 0x80: suba_im(m68_state); break;
case 0x81: cmpa_im(m68_state); break;
case 0x82: sbca_im(m68_state); break;
case 0x83: subd_im(m68_state); break;
case 0x84: anda_im(m68_state); break;
case 0x85: bita_im(m68_state); break;
case 0x86: lda_im(m68_state); break;
case 0x87: sta_im(m68_state); break;
case 0x88: eora_im(m68_state); break;
case 0x89: adca_im(m68_state); break;
case 0x8a: ora_im(m68_state); break;
case 0x8b: adda_im(m68_state); break;
case 0x8c: cmpx_im(m68_state); break;
case 0x8d: bsr(m68_state); break;
case 0x8e: ldx_im(m68_state); break;
case 0x8f: stx_im(m68_state); break;
case 0x90: suba_di(m68_state); break;
case 0x91: cmpa_di(m68_state); break;
case 0x92: sbca_di(m68_state); break;
case 0x93: subd_di(m68_state); break;
case 0x94: anda_di(m68_state); break;
case 0x95: bita_di(m68_state); break;
case 0x96: lda_di(m68_state); break;
case 0x97: sta_di(m68_state); break;
case 0x98: eora_di(m68_state); break;
case 0x99: adca_di(m68_state); break;
case 0x9a: ora_di(m68_state); break;
case 0x9b: adda_di(m68_state); break;
case 0x9c: cmpx_di(m68_state); break;
case 0x9d: jsr_di(m68_state); break;
case 0x9e: ldx_di(m68_state); break;
case 0x9f: stx_di(m68_state); break;
case 0xa0: suba_ix(m68_state); break;
case 0xa1: cmpa_ix(m68_state); break;
case 0xa2: sbca_ix(m68_state); break;
case 0xa3: subd_ix(m68_state); break;
case 0xa4: anda_ix(m68_state); break;
case 0xa5: bita_ix(m68_state); break;
case 0xa6: lda_ix(m68_state); break;
case 0xa7: sta_ix(m68_state); break;
case 0xa8: eora_ix(m68_state); break;
case 0xa9: adca_ix(m68_state); break;
case 0xaa: ora_ix(m68_state); break;
case 0xab: adda_ix(m68_state); break;
case 0xac: cmpx_ix(m68_state); break;
case 0xad: jsr_ix(m68_state); break;
case 0xae: ldx_ix(m68_state); break;
case 0xaf: stx_ix(m68_state); break;
case 0xb0: suba_ex(m68_state); break;
case 0xb1: cmpa_ex(m68_state); break;
case 0xb2: sbca_ex(m68_state); break;
case 0xb3: subd_ex(m68_state); break;
case 0xb4: anda_ex(m68_state); break;
case 0xb5: bita_ex(m68_state); break;
case 0xb6: lda_ex(m68_state); break;
case 0xb7: sta_ex(m68_state); break;
case 0xb8: eora_ex(m68_state); break;
case 0xb9: adca_ex(m68_state); break;
case 0xba: ora_ex(m68_state); break;
case 0xbb: adda_ex(m68_state); break;
case 0xbc: cmpx_ex(m68_state); break;
case 0xbd: jsr_ex(m68_state); break;
case 0xbe: ldx_ex(m68_state); break;
case 0xbf: stx_ex(m68_state); break;
case 0xc0: subb_im(m68_state); break;
case 0xc1: cmpb_im(m68_state); break;
case 0xc2: sbcb_im(m68_state); break;
case 0xc3: addd_im(m68_state); break;
case 0xc4: andb_im(m68_state); break;
case 0xc5: bitb_im(m68_state); break;
case 0xc6: ldb_im(m68_state); break;
case 0xc7: stb_im(m68_state); break;
case 0xc8: eorb_im(m68_state); break;
case 0xc9: adcb_im(m68_state); break;
case 0xca: orb_im(m68_state); break;
case 0xcb: addb_im(m68_state); break;
case 0xcc: ldd_im(m68_state); break;
case 0xcd: std_im(m68_state); break;
case 0xce: ldu_im(m68_state); break;
case 0xcf: stu_im(m68_state); break;
case 0xd0: subb_di(m68_state); break;
case 0xd1: cmpb_di(m68_state); break;
case 0xd2: sbcb_di(m68_state); break;
case 0xd3: addd_di(m68_state); break;
case 0xd4: andb_di(m68_state); break;
case 0xd5: bitb_di(m68_state); break;
case 0xd6: ldb_di(m68_state); break;
case 0xd7: stb_di(m68_state); break;
case 0xd8: eorb_di(m68_state); break;
case 0xd9: adcb_di(m68_state); break;
case 0xda: orb_di(m68_state); break;
case 0xdb: addb_di(m68_state); break;
case 0xdc: ldd_di(m68_state); break;
case 0xdd: std_di(m68_state); break;
case 0xde: ldu_di(m68_state); break;
case 0xdf: stu_di(m68_state); break;
case 0xe0: subb_ix(m68_state); break;
case 0xe1: cmpb_ix(m68_state); break;
case 0xe2: sbcb_ix(m68_state); break;
case 0xe3: addd_ix(m68_state); break;
case 0xe4: andb_ix(m68_state); break;
case 0xe5: bitb_ix(m68_state); break;
case 0xe6: ldb_ix(m68_state); break;
case 0xe7: stb_ix(m68_state); break;
case 0xe8: eorb_ix(m68_state); break;
case 0xe9: adcb_ix(m68_state); break;
case 0xea: orb_ix(m68_state); break;
case 0xeb: addb_ix(m68_state); break;
case 0xec: ldd_ix(m68_state); break;
case 0xed: std_ix(m68_state); break;
case 0xee: ldu_ix(m68_state); break;
case 0xef: stu_ix(m68_state); break;
case 0xf0: subb_ex(m68_state); break;
case 0xf1: cmpb_ex(m68_state); break;
case 0xf2: sbcb_ex(m68_state); break;
case 0xf3: addd_ex(m68_state); break;
case 0xf4: andb_ex(m68_state); break;
case 0xf5: bitb_ex(m68_state); break;
case 0xf6: ldb_ex(m68_state); break;
case 0xf7: stb_ex(m68_state); break;
case 0xf8: eorb_ex(m68_state); break;
case 0xf9: adcb_ex(m68_state); break;
case 0xfa: orb_ex(m68_state); break;
case 0xfb: addb_ex(m68_state); break;
case 0xfc: ldd_ex(m68_state); break;
case 0xfd: std_ex(m68_state); break;
case 0xfe: ldu_ex(m68_state); break;
case 0xff: stu_ex(m68_state); break;
}
#else
(*m6809_main[m68_state->ireg])(m68_state);
#endif /* BIG_SWITCH */
m68_state->icount -= cycles1[m68_state->ireg];
} while( m68_state->icount > 0 );
m68_state->icount -= m68_state->extra_cycles;
m68_state->extra_cycles = 0;
}
return cycles - m68_state->icount; /* NS 970908 */
}
CString PhoneInfoMng::FindPhoneNum(CString csNum)
{
CString head = csNum;
CString kj = csNum;
CString subNum = csNum;
CString fg = csNum;
head.Delete(1,head.GetLength()-1);
if( head == _T('1') && csNum.GetLength() >= 8)
{
kj.Delete(3,kj.GetLength()-3);
}
else if( head == _T('0') )
{
kj = _T("Tel");
}
else
{
if( CSysConfig::Instance().GetLanguage() == ID_CHINESE )
return _T("±¾µØºÅÂë");
else
return _T("Local number");
}
TCHAR strModuleFileName[256];
CString strPath;
memset((void *)strModuleFileName,0,256);
GetModuleFileName(NULL,strModuleFileName,256);
strPath = strModuleFileName;
UINT iPos=-1;
for(int i=strPath.GetLength()-1;i>=0;i--)
{
TCHAR ch = strPath.GetAt(i);
if(ch==L'\\')
{
iPos = i;
break;
}
}
CString strFullPath = strPath.Left(iPos+1) + _T("Tel\\") + kj ;
CFile DialBookFile;
if( !DialBookFile.Open(strFullPath, CFile::modeRead ) )
return _T("");
if( head == _T('1') )
{
subNum.Delete(7,subNum.GetLength()-7);
subNum.Delete(0,3);
int isubNum = _ttol(subNum);
int pos = 29 * isubNum ;
DialBookFile.Seek( pos,CFile::begin );
char buf[28];
DialBookFile.Read(buf,27);
buf[27] = '\0';
CString rts(buf);
rts.Delete(0,7);
rts.TrimRight();
DialBookFile.Close();
return rts;
}
else if( head == _T('0') )
{
CPhoneInfo* pInfo = NULL;
fg.Delete(fg.GetLength()-7,7);
subNum.Delete(subNum.GetLength()-8,8);
for( int h=0;h<m_ObArr.GetSize();h++)
{
pInfo = (CPhoneInfo*)m_ObArr.GetAt(h);
if( pInfo->m_csNum == fg || pInfo->m_csNum == subNum )
return pInfo->m_csName;
}
return _T("");
}
}
BasicType Bytecode_member_ref::result_type() const {
ResultTypeFinder rts(signature());
rts.iterate();
return rts.type();
}
/* Generate interrupts */
static void Interrupt(void)
{
/* the 6805 latches interrupt requests internally, so we don't clear */
/* pending_interrupts until the interrupt is taken, no matter what the */
/* external IRQ pin does. */
#if (1) //HAS_HD63705)
if( (m6805.pending_interrupts & (1<<HD63705_INT_NMI)) != 0)
{
PUSHWORD(m6805.pc);
PUSHBYTE(m6805.x);
PUSHBYTE(m6805.a);
PUSHBYTE(m6805.cc);
SEI;
/* no vectors supported, just do the callback to clear irq_state if needed */
if (m6805.irq_callback)
(*m6805.irq_callback)(0);
RM16( 0x1ffc, &pPC);
change_pc(PC);
m6805.pending_interrupts &= ~(1<<HD63705_INT_NMI);
m6805_ICount -= 11;
}
else if( (m6805.pending_interrupts & ((1<<M6805_IRQ_LINE)|HD63705_INT_MASK)) != 0 ) {
if ( (CC & IFLAG) == 0 ) {
#else
if( (m6805.pending_interrupts & (1<<M6805_IRQ_LINE)) != 0 ) {
if ( (CC & IFLAG) == 0 ) {
#endif
{
/* standard IRQ */
//#if (HAS_HD63705)
// if(SUBTYPE!=SUBTYPE_HD63705)
//#endif
// PC |= ~AMASK;
PUSHWORD(m6805.pc);
PUSHBYTE(m6805.x);
PUSHBYTE(m6805.a);
PUSHBYTE(m6805.cc);
SEI;
/* no vectors supported, just do the callback to clear irq_state if needed */
if (m6805.irq_callback)
(*m6805.irq_callback)(0);
//#if (HAS_HD63705)
if(SUBTYPE==SUBTYPE_HD63705)
{
/* Need to add emulation of other interrupt sources here KW-2/4/99 */
/* This is just a quick patch for Namco System 2 operation */
if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ1))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ1);
RM16( 0x1ff8, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ2))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ2);
RM16( 0x1fec, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_ADCONV))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_ADCONV);
RM16( 0x1fea, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER1))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER1);
RM16( 0x1ff6, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER2))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER2);
RM16( 0x1ff4, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER3))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER3);
RM16( 0x1ff2, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_PCI))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_PCI);
RM16( 0x1ff0, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_SCI))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_SCI);
RM16( 0x1fee, &pPC);
change_pc(PC);
}
}
else
//#endif
{
RM16( 0xffff - 5, &pPC );
change_pc(PC);
}
} // CC & IFLAG
m6805.pending_interrupts &= ~(1<<M6805_IRQ_LINE);
}
m6805_ICount -= 11;
}
}
static void m6805_reset()
{
int (*save_irqcallback)(int) = m6805.irq_callback;
memset(&m6805, 0, sizeof(m6805));
m6805.irq_callback = save_irqcallback;
/* Force CPU sub-type and relevant masks */
m6805.subtype = SUBTYPE_M6805;
SP_MASK = 0x07f;
SP_LOW = 0x060;
/* Initial stack pointer */
S = SP_MASK;
/* IRQ disabled */
SEI;
RM16( 0xfffe , &pPC );
change_pc(PC);
}
void m6805Reset() {
m6805_reset();
}
//static void m6805_init(int ) //int (*irqcallback)(int))
//{
// m6805.irq_callback = irqcallback;
//}
//static void m6805_exit(void)
//{
// /* nothing to do */
//}
void m6805SetIrqLine(int , int state)
{
/* Basic 6805 only has one IRQ line */
/* See HD63705 specific version */
if (m6805.irq_state[0] == state) return;
m6805.irq_state[0] = state;
if (state != CLEAR_LINE)
m6805.pending_interrupts |= 1<<M6805_IRQ_LINE;
}
#include "6805ops.c"
/* execute instructions on this CPU until icount expires */
int m6805Run(int cycles)
{
UINT8 ireg;
m6805_ICount = cycles;
do
{
if (m6805.pending_interrupts != 0)
{
if (SUBTYPE==SUBTYPE_M68705)
{
m68705_Interrupt();
}
else
{
Interrupt();
}
}
ireg=M_RDOP(PC++);
switch( ireg )
{
case 0x00: brset(0x01); break;
case 0x01: brclr(0x01); break;
case 0x02: brset(0x02); break;
case 0x03: brclr(0x02); break;
case 0x04: brset(0x04); break;
case 0x05: brclr(0x04); break;
case 0x06: brset(0x08); break;
case 0x07: brclr(0x08); break;
case 0x08: brset(0x10); break;
case 0x09: brclr(0x10); break;
case 0x0A: brset(0x20); break;
case 0x0B: brclr(0x20); break;
case 0x0C: brset(0x40); break;
case 0x0D: brclr(0x40); break;
case 0x0E: brset(0x80); break;
case 0x0F: brclr(0x80); break;
case 0x10: bset(0x01); break;
case 0x11: bclr(0x01); break;
case 0x12: bset(0x02); break;
case 0x13: bclr(0x02); break;
case 0x14: bset(0x04); break;
case 0x15: bclr(0x04); break;
case 0x16: bset(0x08); break;
case 0x17: bclr(0x08); break;
case 0x18: bset(0x10); break;
case 0x19: bclr(0x10); break;
case 0x1a: bset(0x20); break;
case 0x1b: bclr(0x20); break;
case 0x1c: bset(0x40); break;
case 0x1d: bclr(0x40); break;
case 0x1e: bset(0x80); break;
case 0x1f: bclr(0x80); break;
case 0x20: bra(); break;
case 0x21: brn(); break;
case 0x22: bhi(); break;
case 0x23: bls(); break;
case 0x24: bcc(); break;
case 0x25: bcs(); break;
case 0x26: bne(); break;
case 0x27: beq(); break;
case 0x28: bhcc(); break;
case 0x29: bhcs(); break;
case 0x2a: bpl(); break;
case 0x2b: bmi(); break;
case 0x2c: bmc(); break;
case 0x2d: bms(); break;
case 0x2e: bil(); break;
case 0x2f: bih(); break;
case 0x30: neg_di(); break;
case 0x31: illegal(); break;
case 0x32: illegal(); break;
case 0x33: com_di(); break;
case 0x34: lsr_di(); break;
case 0x35: illegal(); break;
case 0x36: ror_di(); break;
case 0x37: asr_di(); break;
case 0x38: lsl_di(); break;
case 0x39: rol_di(); break;
case 0x3a: dec_di(); break;
case 0x3b: illegal(); break;
case 0x3c: inc_di(); break;
case 0x3d: tst_di(); break;
case 0x3e: illegal(); break;
case 0x3f: clr_di(); break;
case 0x40: nega(); break;
case 0x41: illegal(); break;
case 0x42: illegal(); break;
case 0x43: coma(); break;
case 0x44: lsra(); break;
case 0x45: illegal(); break;
case 0x46: rora(); break;
case 0x47: asra(); break;
case 0x48: lsla(); break;
case 0x49: rola(); break;
case 0x4a: deca(); break;
case 0x4b: illegal(); break;
case 0x4c: inca(); break;
case 0x4d: tsta(); break;
case 0x4e: illegal(); break;
case 0x4f: clra(); break;
case 0x50: negx(); break;
case 0x51: illegal(); break;
case 0x52: illegal(); break;
case 0x53: comx(); break;
case 0x54: lsrx(); break;
case 0x55: illegal(); break;
case 0x56: rorx(); break;
case 0x57: asrx(); break;
case 0x58: aslx(); break;
case 0x59: rolx(); break;
case 0x5a: decx(); break;
case 0x5b: illegal(); break;
case 0x5c: incx(); break;
case 0x5d: tstx(); break;
case 0x5e: illegal(); break;
case 0x5f: clrx(); break;
case 0x60: neg_ix1(); break;
case 0x61: illegal(); break;
case 0x62: illegal(); break;
case 0x63: com_ix1(); break;
case 0x64: lsr_ix1(); break;
case 0x65: illegal(); break;
case 0x66: ror_ix1(); break;
case 0x67: asr_ix1(); break;
case 0x68: lsl_ix1(); break;
case 0x69: rol_ix1(); break;
case 0x6a: dec_ix1(); break;
case 0x6b: illegal(); break;
case 0x6c: inc_ix1(); break;
case 0x6d: tst_ix1(); break;
case 0x6e: illegal(); break;
case 0x6f: clr_ix1(); break;
case 0x70: neg_ix(); break;
case 0x71: illegal(); break;
case 0x72: illegal(); break;
case 0x73: com_ix(); break;
case 0x74: lsr_ix(); break;
case 0x75: illegal(); break;
case 0x76: ror_ix(); break;
case 0x77: asr_ix(); break;
case 0x78: lsl_ix(); break;
case 0x79: rol_ix(); break;
case 0x7a: dec_ix(); break;
case 0x7b: illegal(); break;
case 0x7c: inc_ix(); break;
case 0x7d: tst_ix(); break;
case 0x7e: illegal(); break;
case 0x7f: clr_ix(); break;
case 0x80: rti(); break;
case 0x81: rts(); break;
case 0x82: illegal(); break;
case 0x83: swi(); break;
case 0x84: illegal(); break;
case 0x85: illegal(); break;
case 0x86: illegal(); break;
case 0x87: illegal(); break;
case 0x88: illegal(); break;
case 0x89: illegal(); break;
case 0x8a: illegal(); break;
case 0x8b: illegal(); break;
case 0x8c: illegal(); break;
case 0x8d: illegal(); break;
case 0x8e: illegal(); break;
case 0x8f: illegal(); break;
case 0x90: illegal(); break;
case 0x91: illegal(); break;
case 0x92: illegal(); break;
case 0x93: illegal(); break;
case 0x94: illegal(); break;
case 0x95: illegal(); break;
case 0x96: illegal(); break;
case 0x97: tax(); break;
case 0x98: CLC; break;
case 0x99: SEC; break;
#if IRQ_LEVEL_DETECT
case 0x9a: CLI; if (m6805.irq_state != CLEAR_LINE) m6805.pending_interrupts |= 1<<M6805_IRQ_LINE; break;
#else
case 0x9a: CLI; break;
#endif
case 0x9b: SEI; break;
case 0x9c: rsp(); break;
case 0x9d: nop(); break;
case 0x9e: illegal(); break;
case 0x9f: txa(); break;
case 0xa0: suba_im(); break;
case 0xa1: cmpa_im(); break;
case 0xa2: sbca_im(); break;
case 0xa3: cpx_im(); break;
case 0xa4: anda_im(); break;
case 0xa5: bita_im(); break;
case 0xa6: lda_im(); break;
case 0xa7: illegal(); break;
case 0xa8: eora_im(); break;
case 0xa9: adca_im(); break;
case 0xaa: ora_im(); break;
case 0xab: adda_im(); break;
case 0xac: illegal(); break;
case 0xad: bsr(); break;
case 0xae: ldx_im(); break;
case 0xaf: illegal(); break;
case 0xb0: suba_di(); break;
case 0xb1: cmpa_di(); break;
case 0xb2: sbca_di(); break;
case 0xb3: cpx_di(); break;
case 0xb4: anda_di(); break;
case 0xb5: bita_di(); break;
case 0xb6: lda_di(); break;
case 0xb7: sta_di(); break;
case 0xb8: eora_di(); break;
case 0xb9: adca_di(); break;
case 0xba: ora_di(); break;
case 0xbb: adda_di(); break;
case 0xbc: jmp_di(); break;
case 0xbd: jsr_di(); break;
case 0xbe: ldx_di(); break;
case 0xbf: stx_di(); break;
case 0xc0: suba_ex(); break;
case 0xc1: cmpa_ex(); break;
case 0xc2: sbca_ex(); break;
case 0xc3: cpx_ex(); break;
case 0xc4: anda_ex(); break;
case 0xc5: bita_ex(); break;
case 0xc6: lda_ex(); break;
case 0xc7: sta_ex(); break;
case 0xc8: eora_ex(); break;
case 0xc9: adca_ex(); break;
case 0xca: ora_ex(); break;
case 0xcb: adda_ex(); break;
case 0xcc: jmp_ex(); break;
case 0xcd: jsr_ex(); break;
case 0xce: ldx_ex(); break;
case 0xcf: stx_ex(); break;
case 0xd0: suba_ix2(); break;
case 0xd1: cmpa_ix2(); break;
case 0xd2: sbca_ix2(); break;
case 0xd3: cpx_ix2(); break;
case 0xd4: anda_ix2(); break;
case 0xd5: bita_ix2(); break;
case 0xd6: lda_ix2(); break;
case 0xd7: sta_ix2(); break;
case 0xd8: eora_ix2(); break;
case 0xd9: adca_ix2(); break;
case 0xda: ora_ix2(); break;
case 0xdb: adda_ix2(); break;
case 0xdc: jmp_ix2(); break;
case 0xdd: jsr_ix2(); break;
case 0xde: ldx_ix2(); break;
case 0xdf: stx_ix2(); break;
case 0xe0: suba_ix1(); break;
case 0xe1: cmpa_ix1(); break;
case 0xe2: sbca_ix1(); break;
case 0xe3: cpx_ix1(); break;
case 0xe4: anda_ix1(); break;
case 0xe5: bita_ix1(); break;
case 0xe6: lda_ix1(); break;
case 0xe7: sta_ix1(); break;
case 0xe8: eora_ix1(); break;
case 0xe9: adca_ix1(); break;
case 0xea: ora_ix1(); break;
case 0xeb: adda_ix1(); break;
case 0xec: jmp_ix1(); break;
case 0xed: jsr_ix1(); break;
case 0xee: ldx_ix1(); break;
case 0xef: stx_ix1(); break;
case 0xf0: suba_ix(); break;
case 0xf1: cmpa_ix(); break;
case 0xf2: sbca_ix(); break;
case 0xf3: cpx_ix(); break;
case 0xf4: anda_ix(); break;
case 0xf5: bita_ix(); break;
case 0xf6: lda_ix(); break;
case 0xf7: sta_ix(); break;
case 0xf8: eora_ix(); break;
case 0xf9: adca_ix(); break;
case 0xfa: ora_ix(); break;
case 0xfb: adda_ix(); break;
case 0xfc: jmp_ix(); break;
case 0xfd: jsr_ix(); break;
case 0xfe: ldx_ix(); break;
case 0xff: stx_ix(); break;
}
m6805_ICount -= cycles1[ireg];
m6805.nTotalCycles += cycles1[ireg];
} while( m6805_ICount > 0 );
return cycles - m6805_ICount;
}
// run appropriate function for opcode in memory
void execute_cpu(machine* mch)
{
uint8_t *opcode = &mch->memory[mch->pc++];
uint8_t *memory = mch->memory;
fprintf(stdout, "opcode: %x\n", opcode[0]);
switch(*opcode) {
case 0x02: exit(123);
case 0x12: exit(123);
case 0x22: exit(123);
case 0x32: exit(123);
case 0x42: exit(123);
case 0x52: exit(123);
case 0x62: exit(123);
case 0x72: exit(123);
case 0x92: exit(123);
case 0xB2: exit(123);
case 0xD2: exit(123);
case 0xF2: exit(123);
case 0xEA: return nop(mch, 1);
case 0x1A: return nop(mch, 2); // illegal instruction (nop with 2 cycles)
case 0x7A: return nop(mch, 2); // same as above
case 0x69: return adc_imm(opcode[1], mch);
case 0x65: return adc_zp(opcode[1], mch);
case 0x75: return adc_zpx(opcode[1], mch);
case 0x6D: return adc_abs(opcode[2], opcode[1], mch);
case 0x7D: return adc_absx(opcode[2], opcode[1], mch);
case 0x79: return adc_absy(opcode[2], opcode[1], mch);
case 0x61: return adc_indx(opcode[2], opcode[1], mch);
case 0x71: return adc_indy(opcode[2], opcode[1], mch);
case 0x29: return and_imm(opcode[1], mch);
case 0x25: return and_zp(opcode[1], mch);
case 0x35: return and_zpx(opcode[1], mch);
case 0x2D: return and_abs(opcode[2], opcode[1], mch);
case 0x3D: return and_absx(opcode[2], opcode[1], mch);
case 0x39: return and_absy(opcode[2], opcode[1], mch);
case 0x21: return and_indx(opcode[2], opcode[1], mch);
case 0x31: return and_indy(opcode[2], opcode[1], mch);
case 0x0A: return asl_acc(mch);
case 0x06: return asl_zp(opcode[1], mch);
case 0x16: return asl_zpx(opcode[1], mch);
case 0x0E: return asl_abs(opcode[2], opcode[1], mch);
case 0x1E: return asl_absx(opcode[2], opcode[1], mch);
case 0x90: return branch_clear(opcode[2], opcode[1], mch, 0b00000001);
case 0xB0: return branch_set(opcode[2], opcode[1], mch, 0b00000001);
case 0xF0: return branch_set(opcode[2], opcode[1], mch, 0b00000010);
case 0x24: return bit_zp(opcode[1], mch);
case 0x2C: return bit_abs(opcode[2], opcode[1], mch);
case 0x30: return branch_set(opcode[2], opcode[1], mch, 0b10000000);
case 0xD0: return branch_clear(opcode[2], opcode[1], mch, 0b00000010);
case 0x10: return branch_clear(opcode[2], opcode[1], mch, 0b10000000);
case 0x00: return brk(mch);
case 0x50: return branch_clear(opcode[2], opcode[1], mch, 0b01000000);
case 0x70: return branch_set(opcode[2], opcode[1], mch, 0b01000000);
case 0x18: return clc(mch);
case 0x58: return cli(mch);
case 0xB8: return clv(mch);
case 0xC9: return cmp_imm(opcode[1], mch);
case 0xC5: return cmp_zp(opcode[1], mch);
case 0xD5: return cmp_zpx(opcode[1], mch);
case 0xCD: return cmp_abs(opcode[2], opcode[1], mch, 0, 0);
case 0xDD: return cmp_abs(opcode[2], opcode[1], mch, 1, mch->X);
case 0xD9: return cmp_abs(opcode[2], opcode[1], mch, 1, mch->Y);
case 0xC1: return cmp_indy(opcode[2], opcode[1], mch);
case 0xD1: return cmp_indx(opcode[2], opcode[1], mch);
case 0xE0: return cpx_imm(opcode[1], mch);
case 0xE4: return cpx_zp(opcode[1], mch);
case 0xEC: return cpx_abs(opcode[2], opcode[1], mch);
case 0xC0: return cpy_imm(opcode[1], mch);
case 0xC4: return cpy_zp(opcode[1], mch);
case 0xCC: return cpy_abs(opcode[2], opcode[1], mch);
case 0xC6: return dec_zp(opcode[1], mch);
case 0xD6: return dec_zpx(opcode[1], mch);
case 0xCE: return dec_abs(opcode[2], opcode[1], mch);
case 0xDE: return dec_absx(opcode[2], opcode[1], mch);
case 0xCA: return dex(mch);
case 0x88: return dey(mch);
case 0x49: return eor_imm(opcode[1], mch);
case 0x45: return eor_zp(opcode[1], mch);
case 0x55: return eor_zpx(opcode[1], mch);
case 0x4D: return eor_abs(opcode[2], opcode[1], mch);
case 0x5D: return eor_absx(opcode[2], opcode[1], mch);
case 0x59: return eor_absy(opcode[2], opcode[1], mch);
case 0x41: return eor_indx(opcode[2], opcode[1], mch);
case 0x51: return eor_indy(opcode[2], opcode[1], mch);
case 0xE6: return inc_zp(opcode[1], mch, 0, 0);
case 0xF6: return inc_zp(opcode[1], mch, 1, mch->X);
case 0xEE: return inc_abs(opcode[2], opcode[1], mch, 0, 0);
case 0xFE: return inc_abs(opcode[2], opcode[1], mch, 1, mch->X);
case 0xE8: return inx(mch);
case 0xC8: return iny(mch);
case 0x4C: return jmp_abs(opcode[2], opcode[1], mch);
case 0x6C: return jmp_ind(opcode[2], opcode[1], mch);
case 0x20: return jsr(opcode[2], opcode[1], mch);
case 0xA9: return lda_imm(opcode[1], mch);
case 0xA5: return lda_zp(opcode[1], mch, 0, 0);
case 0xB5: return lda_zp(opcode[1], mch, 1, mch->X);
case 0xAD: return lda_abs(opcode[2], opcode[1], mch, 0, 0);
case 0xBD: return lda_abs(opcode[2], opcode[1], mch, 1, mch->X);
case 0xB9: return lda_abs(opcode[2], opcode[1], mch, 1, mch->Y);
case 0xA1: return lda_indx(opcode[2], opcode[1], mch);
case 0xB1: return lda_indy(opcode[2], opcode[1], mch);
case 0xA2: return ldx_imm(opcode[1], mch);
case 0xA6: return ldx_zp(opcode[1], mch, 0, 0);
case 0xB6: return ldx_zp(opcode[1], mch, 1, mch->X);
case 0xAE: return ldx_abs(opcode[2], opcode[1], mch, 0, 0);
case 0xBE: return ldx_abs(opcode[2], opcode[1], mch, 1, mch->X);
case 0xA0: return ldy_imm(opcode[1], mch);
case 0xA4: return ldy_zp(opcode[1], mch, 0, 0);
case 0xB4: return ldy_zp(opcode[1], mch, 1, mch->X);
case 0xAC: return ldy_abs(opcode[2], opcode[1], mch, 0, 0);
case 0xBC: return ldy_abs(opcode[2], opcode[1], mch, 1, mch->X);
case 0x4A: return lsr_acc(mch);
case 0x46: return lsr_zp(opcode[1], mch);
case 0x56: return lsr_zpx(opcode[1], mch);
case 0x4E: return lsr_abs(opcode[2], opcode[1], mch);
case 0x5E: return lsr_absx(opcode[2], opcode[1], mch);
case 0x09: return or_imm(opcode[1], mch);
case 0x05: return or_zp(opcode[1], mch);
case 0x15: return or_zpx(opcode[1], mch);
case 0x0D: return or_abs(opcode[2], opcode[1], mch);
case 0x1D: return or_absx(opcode[2], opcode[1], mch);
case 0x19: return or_absy(opcode[2], opcode[1], mch);
case 0x01: return or_indx(opcode[2], opcode[1], mch);
case 0x11: return or_indy(opcode[2], opcode[1], mch);
case 0x48: return pha(mch);
case 0x08: return php(mch);
case 0x68: return pla(mch);
case 0x28: return plp(mch);
case 0x40: return rti(mch);
case 0x60: return rts(mch);
case 0x78: return sei(mch);
case 0x38: return sec(mch);
case 0xAA: return tax(mch);
case 0xA8: return tay(mch);
case 0x8A: return txa(mch);
case 0x98: return tya(mch);
default:
fprintf(stdout, "unimplemented opcode!\n");
fprintf(stdout, "opcode in question: %x\n", opcode[0]);
exit(1);
break;
}
}
bool test_4(void) {
rts(1);
tx(1);
_delay_us(1);
return rx() == 0;
}
