static int
rtw_pci_attach(device_t dev)
{
struct rtw_softc *sc = device_get_softc(dev);
struct rtw_regs *regs = &sc->sc_regs;
int i, error;
/*
* No power management hooks.
* XXX Maybe we should add some!
*/
sc->sc_flags |= RTW_F_ENABLED;
sc->sc_rev = pci_get_revid(dev);
#ifndef BURN_BRIDGES
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
uint32_t mem, port, irq;
mem = pci_read_config(dev, RTW_PCI_MMBA, 4);
port = pci_read_config(dev, RTW_PCI_IOBA, 4);
irq = pci_read_config(dev, PCIR_INTLINE, 4);
device_printf(dev, "chip is in D%d power mode "
"-- setting to D0\n", pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
pci_write_config(dev, RTW_PCI_MMBA, mem, 4);
pci_write_config(dev, RTW_PCI_IOBA, port, 4);
pci_write_config(dev, PCIR_INTLINE, irq, 4);
}
#endif /* !BURN_BRIDGES */
/* Enable PCI bus master */
pci_enable_busmaster(dev);
/* Allocate IO memory/port */
for (i = 0; i < NELEM(rtw_pci_regs); ++i) {
regs->r_rid = rtw_pci_regs[i].reg_rid;
regs->r_type = rtw_pci_regs[i].reg_type;
regs->r_res = bus_alloc_resource_any(dev, regs->r_type,
®s->r_rid, RF_ACTIVE);
if (regs->r_res != NULL)
break;
}
if (regs->r_res == NULL) {
device_printf(dev, "can't allocate IO mem/port\n");
return ENXIO;
}
regs->r_bh = rman_get_bushandle(regs->r_res);
regs->r_bt = rman_get_bustag(regs->r_res);
error = rtw_attach(dev);
if (error)
rtw_pci_detach(dev);
return error;
}
void
rtw_pci_attach(struct device *parent, struct device *self, void *aux)
{
struct rtw_pci_softc *psc = (void *) self;
struct rtw_softc *sc = &psc->psc_rtw;
struct rtw_regs *regs = &sc->sc_regs;
struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
const char *intrstr = NULL;
bus_space_tag_t iot, memt;
bus_space_handle_t ioh, memh;
bus_size_t iosize, memsize;
int ioh_valid, memh_valid;
psc->psc_pc = pa->pa_pc;
psc->psc_pcitag = pa->pa_tag;
/*
* No power management hooks.
* XXX Maybe we should add some!
*/
sc->sc_flags |= RTW_F_ENABLED;
/*
* Get revision info, and set some chip-specific variables.
*/
sc->sc_rev = PCI_REVISION(pa->pa_class);
pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
/*
* Map the device.
*/
ioh_valid = (pci_mapreg_map(pa, RTW_PCI_IOBA,
PCI_MAPREG_TYPE_IO, 0,
&iot, &ioh, NULL, &iosize, 0) == 0);
memh_valid = (pci_mapreg_map(pa, RTW_PCI_MMBA,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&memt, &memh, NULL, &memsize, 0) == 0);
if (memh_valid) {
regs->r_bt = memt;
regs->r_bh = memh;
psc->psc_mapsize = memsize;
} else if (ioh_valid) {
regs->r_bt = iot;
regs->r_bh = ioh;
psc->psc_mapsize = iosize;
} else {
printf(": unable to map device registers\n");
return;
}
sc->sc_dmat = pa->pa_dmat;
/*
* Map and establish our interrupt.
*/
if (pci_intr_map(pa, &psc->psc_ih)) {
printf(": unable to map interrupt\n");
return;
}
intrstr = pci_intr_string(pc, psc->psc_ih);
psc->psc_intrcookie = pci_intr_establish(pc, psc->psc_ih, IPL_NET,
rtw_intr, sc, sc->sc_dev.dv_xname);
if (psc->psc_intrcookie == NULL) {
printf(": unable to establish interrupt");
if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
return;
}
printf(": %s\n", intrstr);
sc->sc_enable = rtw_pci_enable;
sc->sc_disable = rtw_pci_disable;
/*
* Finish off the attach.
*/
rtw_attach(sc);
}
void
rtw_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct rtw_cardbus_softc *csc = (void *)self;
struct rtw_softc *sc = &csc->sc_rtw;
struct rtw_regs *regs = &sc->sc_regs;
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
bus_addr_t adr;
int rev;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_pc = ca->ca_pc;
/*
* Power management hooks.
*/
sc->sc_enable = rtw_cardbus_enable;
sc->sc_disable = rtw_cardbus_disable;
sc->sc_power = rtw_cardbus_power;
sc->sc_intr_ack = rtw_cardbus_intr_ack;
/* Get revision info. */
rev = PCI_REVISION(ca->ca_class);
RTW_DPRINTF(RTW_DEBUG_ATTACH,
("%s: pass %d.%d signature %08x\n", sc->sc_dev.dv_xname,
(rev >> 4) & 0xf, rev & 0xf,
pci_conf_read(ca->ca_pc, csc->sc_tag, 0x80)));
/*
* Map the device.
*/
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
if (Cardbus_mapreg_map(ct, RTW_PCI_MMBA,
PCI_MAPREG_TYPE_MEM, 0, ®s->r_bt, ®s->r_bh, &adr,
&csc->sc_mapsize) == 0) {
RTW_DPRINTF(RTW_DEBUG_ATTACH,
("%s: %s mapped %lu bytes mem space\n",
sc->sc_dev.dv_xname, __func__, (long)csc->sc_mapsize));
csc->sc_cben = CARDBUS_MEM_ENABLE;
csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
csc->sc_bar_reg = RTW_PCI_MMBA;
csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
} else if (Cardbus_mapreg_map(ct, RTW_PCI_IOBA,
PCI_MAPREG_TYPE_IO, 0, ®s->r_bt, ®s->r_bh, &adr,
&csc->sc_mapsize) == 0) {
RTW_DPRINTF(RTW_DEBUG_ATTACH,
("%s: %s mapped %lu bytes I/O space\n",
sc->sc_dev.dv_xname, __func__, (long)csc->sc_mapsize));
csc->sc_cben = CARDBUS_IO_ENABLE;
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
csc->sc_bar_reg = RTW_PCI_IOBA;
csc->sc_bar_val = adr | PCI_MAPREG_TYPE_IO;
} else {
printf("%s: unable to map device registers\n",
sc->sc_dev.dv_xname);
return;
}
/*
* Bring the chip out of powersave mode and initialize the
* configuration registers.
*/
rtw_cardbus_setup(csc);
/* Remember which interrupt line. */
csc->sc_intrline = ca->ca_intrline;
printf(": irq %d\n", csc->sc_intrline);
/*
* Finish off the attach.
*/
rtw_attach(sc);
rtw_cardbus_funcregen(regs, 1);
RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_INTR);
RTW_WRITE(regs, RTW_FER, RTW_FER_INTR);
/*
* Power down the socket.
*/
Cardbus_function_disable(csc->sc_ct);
}
void
rtw_pci_attach(struct device *parent, struct device *self, void *aux)
{
struct rtw_pci_softc *psc = (void *) self;
struct rtw_softc *sc = &psc->psc_rtw;
struct rtw_regs *regs = &sc->sc_regs;
struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
const char *intrstr = NULL;
bus_space_tag_t iot, memt;
bus_space_handle_t ioh, memh;
int ioh_valid, memh_valid;
pcireg_t reg;
int pmreg;
psc->psc_pc = pa->pa_pc;
psc->psc_pcitag = pa->pa_tag;
/*
* No power management hooks.
* XXX Maybe we should add some!
*/
sc->sc_flags |= RTW_F_ENABLED;
/*
* Get revision info, and set some chip-specific variables.
*/
sc->sc_rev = PCI_REVISION(pa->pa_class);
/*
* Check to see if the device is in power-save mode, and
* being it out if necessary.
*
* XXX This code comes almost verbatim from if_tlp_pci.c. I do
* not understand it. Tulip clears the "sleep mode" bit in the
* CFDA register, first. There is an equivalent (?) register at the
* same place in the ADM8211, but the docs do not assign its bits
* any meanings. -dcy
*/
if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) {
reg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR);
switch (reg & PCI_PMCSR_STATE_MASK) {
case PCI_PMCSR_STATE_D1:
case PCI_PMCSR_STATE_D2:
printf(": waking up from power state D%d\n",
reg & PCI_PMCSR_STATE_MASK);
pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR,
(reg & ~PCI_PMCSR_STATE_MASK) |
PCI_PMCSR_STATE_D0);
break;
case PCI_PMCSR_STATE_D3:
/*
* The card has lost all configuration data in
* this state, so punt.
*/
printf(": unable to wake up from power state D3, "
"reboot required.\n");
pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR,
(reg & ~PCI_PMCSR_STATE_MASK) |
PCI_PMCSR_STATE_D0);
return;
}
}
/*
* Map the device.
*/
ioh_valid = (pci_mapreg_map(pa, RTW_PCI_IOBA,
PCI_MAPREG_TYPE_IO, 0,
&iot, &ioh, NULL, NULL, 0) == 0);
memh_valid = (pci_mapreg_map(pa, RTW_PCI_MMBA,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&memt, &memh, NULL, NULL, 0) == 0);
if (memh_valid) {
regs->r_bt = memt;
regs->r_bh = memh;
} else if (ioh_valid) {
regs->r_bt = iot;
regs->r_bh = ioh;
} else {
printf(": unable to map device registers\n");
return;
}
sc->sc_dmat = pa->pa_dmat;
/*
* Map and establish our interrupt.
*/
if (pci_intr_map(pa, &psc->psc_ih)) {
printf(": unable to map interrupt\n");
return;
}
intrstr = pci_intr_string(pc, psc->psc_ih);
psc->psc_intrcookie = pci_intr_establish(pc, psc->psc_ih, IPL_NET,
rtw_intr, sc, sc->sc_dev.dv_xname);
if (psc->psc_intrcookie == NULL) {
printf(": unable to establish interrupt");
if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
return;
}
printf(": %s\n", intrstr);
sc->sc_enable = rtw_pci_enable;
sc->sc_disable = rtw_pci_disable;
/*
* Finish off the attach.
*/
rtw_attach(sc);
}
