void __init s5pv210_register_clocks(void)
{
int ptr;
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
s3c_register_clksrc(sclk_tv[ptr], 1);
for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
s3c_register_clksrc(clksrc_cdev[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
s3c_disable_clocks(clk_cdev[ptr], 1);
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
}
void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
fdiv_fn get_fdiv)
{
int ptr;
/* s3c2443 parents h and p clocks from prediv */
clk_h.parent = &clk_prediv;
clk_p.parent = &clk_prediv;
clk_usb_bus.parent = &clk_usb_bus_host.clk;
clk_epll.parent = &clk_epllref.clk;
s3c24xx_register_baseclocks(xtal);
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_register_clksrc(clksrcs[ptr], 1);
s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
/* See s3c2443/etc notes on disabling clocks at init time */
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c2443_common_setup_clocks(get_mpll, get_fdiv);
}
void __init s5pv210_register_clocks(void)
{
struct clk *clkp;
int ret;
int ptr;
ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
if (ret > 0)
printk(KERN_ERR "Failed to register %u clocks\n", ret);
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
clkp = init_clocks_disable;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
(clkp->enable)(clkp, 0);
}
s3c_pwmclk_init();
}
/**
* s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
* @xtal: The rate for the clock crystal feeding the PLLs.
* @armclk_divlimit: Divisor mask for ARMCLK.
*
* Register the clocks for the S3C6400 and S3C6410 SoC range, such
* as ARMCLK as well as the necessary parent clocks.
*
* This call does not setup the clocks, which is left to the
* s3c64xx_setup_clocks() call which may be needed by the cpufreq
* or resume code to re-set the clocks if the bootloader has changed
* them.
*/
void __init s3c64xx_register_clocks(unsigned long xtal,
unsigned armclk_divlimit)
{
unsigned int cnt;
armclk_mask = armclk_divlimit;
s3c24xx_register_baseclocks(xtal);
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
s3c_disable_clocks(clk_cdev[cnt], 1);
s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
s3c_register_clksrc(clksrc_cdev[cnt], 1);
clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
s3c_pwmclk_init();
}
void __init s5p6440_register_clocks(void)
{
int ptr;
unsigned int cnt;
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
s3c_disable_clocks(clk_cdev[cnt], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
s3c_register_clksrc(clksrc_cdev[ptr], 1);
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
s3c24xx_register_clock(&dummy_apb_pclk);
}
void __init exynos4_register_clocks(void)
{
int ptr;
s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
s3c_register_clksrc(exynos4_sysclks[ptr], 1);
for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
register_syscore_ops(&exynos4_clock_syscore_ops);
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
}
void __init s5p6450_register_clocks(void)
{
struct clk *clkp;
struct clksrc_clk *clks;
int ret;
int ptr;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrc_audio, ARRAY_SIZE(clksrc_audio));
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
clkp = init_clocks_disable;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
(clkp->enable)(clkp, 0);
}
clks = clksrcs + 1; // A one is added here to intensionally keep the sclk_mali clk enabled.
for (ptr = 0; ptr < (ARRAY_SIZE(clksrcs)-1); ptr++,clks++)
{
clks->clk.enable(&clks->clk,0);
}
s3c_pwmclk_init();
}
static void exynos4212_clock_init(void)
{
int ptr;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks_4212); ptr++)
s3c_register_clksrc(sysclks_4212[ptr], 1);
s3c_register_clksrc(clksrcs_4212, ARRAY_SIZE(clksrcs_4212));
s3c_register_clocks(init_clocks_off_4212, ARRAY_SIZE(init_clocks_off_4212));
s3c_disable_clocks(init_clocks_off_4212, ARRAY_SIZE(init_clocks_off_4212));
}
void __init exynos4210_register_clocks(void)
{
int ptr;
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
exynos4_clk_mout_mpll.reg_src.shift = 8;
exynos4_clk_mout_mpll.reg_src.size = 1;
exynos4_clk_aclk_200.sources = &exynos4_clkset_aclk;
exynos4_clk_aclk_200.reg_src.reg = EXYNOS4_CLKSRC_TOP0;
exynos4_clk_aclk_200.reg_src.shift = 12;
exynos4_clk_aclk_200.reg_src.size = 1;
exynos4_clk_aclk_200.reg_div.reg = EXYNOS4_CLKDIV_TOP;
exynos4_clk_aclk_200.reg_div.shift = 0;
exynos4_clk_aclk_200.reg_div.size = 3;
exynos4_clk_fimg2d.enable = exynos4_clk_ip_image_ctrl;
exynos4_clk_fimg2d.ctrlbit = (1 << 3) | (1 << 0);
exynos4_clk_mout_g2d0.reg_src.reg = EXYNOS4_CLKSRC_IMAGE;
exynos4_clk_mout_g2d0.reg_src.shift = 0;
exynos4_clk_mout_g2d0.reg_src.size = 1;
exynos4_clk_mout_g2d1.reg_src.reg = EXYNOS4_CLKSRC_IMAGE;
exynos4_clk_mout_g2d1.reg_src.shift = 4;
exynos4_clk_mout_g2d1.reg_src.size = 1;
exynos4_clk_sclk_fimg2d.reg_src.reg = EXYNOS4_CLKSRC_IMAGE;
exynos4_clk_sclk_fimg2d.reg_src.shift = 8;
exynos4_clk_sclk_fimg2d.reg_src.size = 1;
exynos4_clk_sclk_fimg2d.reg_div.reg = EXYNOS4_CLKDIV_IMAGE;
exynos4_clk_sclk_fimg2d.reg_div.shift = 0;
exynos4_clk_sclk_fimg2d.reg_div.size = 4;
exynos4_init_dmaclocks[2].parent = &exynos4_init_dmaclocks[1];
exynos4_epll_ops.get_rate = exynos4210_epll_get_rate;
exynos4_epll_ops.set_rate = exynos4210_epll_set_rate;
exynos4_vpll_ops.get_rate = exynos4210_vpll_get_rate;
exynos4_vpll_ops.set_rate = exynos4210_vpll_set_rate;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
register_syscore_ops(&exynos4210_clock_syscore_ops);
}
static void exynos4210_clock_init(void)
{
s3c_register_clksrc(clksrcs_4210, ARRAY_SIZE(clksrcs_4210));
s3c_register_clocks(init_clocks_off_4210, ARRAY_SIZE(init_clocks_off_4210));
s3c_disable_clocks(init_clocks_off_4210, ARRAY_SIZE(init_clocks_off_4210));
}
void __init exynos_register_audss_clocks(void)
{
int ptr;
for (ptr = 0; ptr < ARRAY_SIZE(exynos_audss_clks); ptr++)
s3c_register_clksrc(exynos_audss_clks[ptr], 1);
s3c_register_clocks(exynos_init_audss_clocks, ARRAY_SIZE(exynos_init_audss_clocks));
clk_set_rate(&clk_fout_epll, 192000000);
clk_enable(&clk_fout_epll);
/* Audio subsystem interrupt enable */
writel(1, S5P_VA_AUDSS+EXYNOS5260_AUDSS_CPU_INTR_OFFSET);
/* enable interrupt of ADMA in audss */
writel((1<<6), S5P_VA_AUDSS+EXYNOS5260_AUDSS_INTR_ENABLE_OFFSET);
/* s/w reset AUDSS IPs */
writel(0xf3e, S5P_VA_AUDSS+EXYNOS5260_AUDSS_SWRESET_OFFSET);
writel(0xf3f, S5P_VA_AUDSS+EXYNOS5260_AUDSS_SWRESET_OFFSET);
#if 0
/* all clock for aud should be disable at the init time
this should be enable */
s3c_disable_clocks(exynos_init_audss_clocks, ARRAY_SIZE(exynos_init_audss_clocks));
/* turn clocks off. out of muxes of CMU_AUD */
s3c_disable_clocks(&exynos_clk_aud_pll_user.clk, 1);
s3c_disable_clocks(&exynos_clk_sclk_aud_i2s.clk, 1);
s3c_disable_clocks(&exynos_clk_sclk_aud_pcm.clk, 1);
#endif
}
void __init s3c2443_init_clocks(int xtal)
{
unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
int ptr;
clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
clk_epll.parent = &clk_epllref.clk;
s3c2443_common_init_clocks(xtal, s3c2443_get_mpll,
armdiv, ARRAY_SIZE(armdiv),
S3C2443_CLKDIV0_ARMDIV_MASK);
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_register_clksrc(clksrcs[ptr], 1);
/* We must be careful disabling the clocks we are not intending to
* be using at boot time, as subsystems such as the LCD which do
* their own DMA requests to the bus can cause the system to lockup
* if they where in the middle of requesting bus access.
*
* Disabling the LCD clock if the LCD is active is very dangerous,
* and therefore the bootloader should be careful to not enable
* the LCD clock if it is not needed.
*/
/* install (and disable) the clocks we do not need immediately */
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
s3c_pwmclk_init();
}
/**
* s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
* @xtal: The rate for the clock crystal feeding the PLLs.
* @armclk_divlimit: Divisor mask for ARMCLK.
*
* Register the clocks for the S3C6400 and S3C6410 SoC range, such
* as ARMCLK as well as the necessary parent clocks.
*
* This call does not setup the clocks, which is left to the
* s3c6400_setup_clocks() call which may be needed by the cpufreq
* or resume code to re-set the clocks if the bootloader has changed
* them.
*/
void __init s3c64xx_register_clocks(unsigned long xtal,
unsigned armclk_divlimit)
{
struct clk *clkp;
int ret;
int ptr;
armclk_mask = armclk_divlimit;
s3c24xx_register_baseclocks(xtal);
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
clkp = init_clocks_disable;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
(clkp->enable)(clkp, 0);
}
s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_pwmclk_init();
}
void __init exynos4_register_clocks(void)
{
int ptr;
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_pwmclk_init();
}
void __init exynos4210_register_clocks(void)
{
int ptr;
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
exynos4_clk_mout_mpll.reg_src.shift = 8;
exynos4_clk_mout_mpll.reg_src.size = 1;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
register_syscore_ops(&exynos4210_clock_syscore_ops);
}
void __init s5p6442_register_clocks(void)
{
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_pwmclk_init();
}
void __init exynos_register_audss_clocks(void)
{
int ptr;
for (ptr = 0; ptr < ARRAY_SIZE(exynos_audss_clks); ptr++)
s3c_register_clksrc(exynos_audss_clks[ptr], 1);
s3c_register_clocks(exynos_init_audss_clocks, ARRAY_SIZE(exynos_init_audss_clocks));
s3c_disable_clocks(exynos_init_audss_clocks, ARRAY_SIZE(exynos_init_audss_clocks));
}
void __init s5pv210_register_clocks(void)
{
int ptr;
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
/* Register DMA Clock */
s3c_register_clocks(init_dmaclocks, ARRAY_SIZE(init_dmaclocks));
s3c_disable_clocks(init_dmaclocks, ARRAY_SIZE(init_dmaclocks));
s3c_pwmclk_init();
}
void __init s5pv210_register_clocks(void)
{
int ret;
int ptr;
ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
if (ret > 0)
printk(KERN_ERR "Failed to register %u clocks\n", ret);
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_disable, ARRAY_SIZE(init_clocks_disable));
s3c_register_clocks(init_dmaclocks, ARRAY_SIZE(init_dmaclocks));
s3c_disable_clocks(init_clocks_disable, ARRAY_SIZE(init_clocks_disable));
s3c_disable_clocks(init_dmaclocks, ARRAY_SIZE(init_dmaclocks));
s3c_pwmclk_init();
}
void __init exynos4_register_clocks(void)
{
int ptr;
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
s3c_register_clksrc(sclk_tv[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
register_syscore_ops(&exynos4_clock_syscore_ops);
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
}
void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
unsigned int *divs, int nr_divs,
int divmask)
{
int ptr;
armdiv = divs;
nr_armdiv = nr_divs;
armdivmask = divmask;
/* s3c2443 parents h clock from prediv */
clk_h.parent = &clk_prediv;
clk_h.ops = &clk_h_ops;
/* and p clock from h clock */
clk_p.parent = &clk_h;
clk_p.ops = &clk_p_ops;
clk_usb_bus.parent = &clk_usb_bus_host.clk;
clk_epll.parent = &clk_epllref.clk;
s3c24xx_register_baseclocks(xtal);
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_register_clksrc(clksrcs[ptr], 1);
s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
/* See s3c2443/etc notes on disabling clocks at init time */
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
s3c2443_common_setup_clocks(get_mpll);
}
/**
* s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
* @xtal: The rate for the clock crystal feeding the PLLs.
* @armclk_divlimit: Divisor mask for ARMCLK.
*
* Register the clocks for the S3C6400 and S3C6410 SoC range, such
* as ARMCLK as well as the necessary parent clocks.
*
* This call does not setup the clocks, which is left to the
* s3c6400_setup_clocks() call which may be needed by the cpufreq
* or resume code to re-set the clocks if the bootloader has changed
* them.
*/
void __init s3c64xx_register_clocks(unsigned long xtal,
unsigned armclk_divlimit)
{
armclk_mask = armclk_divlimit;
s3c24xx_register_baseclocks(xtal);
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_pwmclk_init();
}
void __init s3c2416_init_clocks(int xtal)
{
u32 epllcon = __raw_readl(S3C2443_EPLLCON);
u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
int ptr;
/* s3c2416 EPLL compatible with s3c64xx */
clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
clk_epll.parent = &clk_epllref.clk;
s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_register_clksrc(clksrcs[ptr], 1);
s3c_pwmclk_init();
}
void __init s3c2416_init_clocks(int xtal)
{
u32 epllcon = __raw_readl(S3C2443_EPLLCON);
u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
int ptr;
/* s3c2416 EPLL compatible with s3c64xx */
clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
clk_epll.parent = &clk_epllref.clk;
s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
armdiv, ARRAY_SIZE(armdiv),
S3C2416_CLKDIV0_ARMDIV_MASK);
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_register_clksrc(clksrcs[ptr], 1);
s3c24xx_register_clock(&hsmmc0_clk);
clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
s3c_pwmclk_init();
}
void __init exynos4212_register_clocks(void)
{
int ptr;
unsigned int tmp;
/* usbphy1 is removed in exynos 4212 */
exynos4_clkset_group_list[4] = NULL;
/* mout_mpll_user is used instead of mout_mpll in exynos 4212 */
exynos4_clkset_group_list[6] = &exynos4212_clk_mout_mpll_user.clk;
exynos4_clkset_aclk_top_list[0] = &exynos4212_clk_mout_mpll_user.clk;
exynos4_clkset_mout_mfc0_list[0] = &exynos4212_clk_mout_mpll_user.clk;
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_mout_mpll.reg_src.shift = 12;
exynos4_clk_mout_mpll.reg_src.size = 1;
exynos4_clk_aclk_200.sources = &exynos4212_clkset_aclk_200;
exynos4_clk_aclk_200.reg_src.reg = EXYNOS4_CLKSRC_TOP1;
exynos4_clk_aclk_200.reg_src.shift = 20;
exynos4_clk_aclk_200.reg_src.size = 1;
exynos4_clk_fimg2d.enable = exynos4_clk_ip_dmc_ctrl;
exynos4_clk_fimg2d.ctrlbit = (1 << 23);
exynos4_clk_mout_g2d0.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_mout_g2d0.reg_src.shift = 20;
exynos4_clk_mout_g2d0.reg_src.size = 1;
exynos4_clk_mout_g2d1.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_mout_g2d1.reg_src.shift = 24;
exynos4_clk_mout_g2d1.reg_src.size = 1;
exynos4_clk_sclk_fimg2d.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_sclk_fimg2d.reg_src.shift = 28;
exynos4_clk_sclk_fimg2d.reg_src.size = 1;
exynos4_clk_sclk_fimg2d.reg_div.reg = EXYNOS4_CLKDIV_DMC1;
exynos4_clk_sclk_fimg2d.reg_div.shift = 0;
exynos4_clk_sclk_fimg2d.reg_div.size = 4;
exynos4_epll_ops.get_rate = exynos4212_epll_get_rate;
exynos4_epll_ops.set_rate = exynos4212_epll_set_rate;
exynos4_vpll_ops.get_rate = exynos4212_vpll_get_rate;
exynos4_vpll_ops.set_rate = exynos4212_vpll_set_rate;
for (ptr = 0; ptr < ARRAY_SIZE(exynos4212_sysclks); ptr++)
s3c_register_clksrc(exynos4212_sysclks[ptr], 1);
s3c_register_clksrc(exynos4212_clksrcs, ARRAY_SIZE(exynos4212_clksrcs));
s3c_register_clocks(exynos4212_init_clocks, ARRAY_SIZE(exynos4212_init_clocks));
s3c_register_clocks(exynos4212_init_clocks_off, ARRAY_SIZE(exynos4212_init_clocks_off));
s3c_disable_clocks(exynos4212_init_clocks_off, ARRAY_SIZE(exynos4212_init_clocks_off));
s3c_register_clksrc(&exynos4212_clk_isp_srcs_div0, 1);
s3c_register_clksrc(exynos4212_clk_isp_srcs, ARRAY_SIZE(exynos4212_clk_isp_srcs));
s3c_register_clocks(exynos4212_clk_isp, ARRAY_SIZE(exynos4212_clk_isp));
s3c_disable_clocks(&exynos4212_clk_isp_srcs[3].clk, 1);
s3c_disable_clocks(&exynos4212_clk_isp_srcs[4].clk, 1);
s3c_disable_clocks(&exynos4212_clk_isp_srcs[5].clk, 1);
s3c_disable_clocks(&exynos4212_clk_isp_srcs[6].clk, 1);
/* To save power,
* Disable CLKOUT of LEFTBUS, RIGHTBUS, TOP, DMC, CPU and ISP
*/
for (ptr = 0 ; ptr < ARRAY_SIZE(exynos4x12_cmu_config) ; ptr++) {
tmp = __raw_readl(exynos4x12_cmu_config[ptr].reg);
tmp &= ~(0x1 << 16);
tmp |= (exynos4x12_cmu_config[ptr].val << 16);
__raw_writel(tmp, exynos4x12_cmu_config[ptr].reg);
}
register_syscore_ops(&exynos4212_clock_syscore_ops);
}
void __init exynos4212_register_clocks(void)
{
int ptr;
/* usbphy1 is removed in exynos 4212 */
exynos4_clkset_group_list[4] = NULL;
/* mout_mpll_user is used instead of mout_mpll in exynos 4212 */
exynos4_clkset_group_list[6] = &exynos4212_clk_mout_mpll_user.clk;
exynos4_clkset_aclk_top_list[0] = &exynos4212_clk_mout_mpll_user.clk;
exynos4_clkset_mout_mfc0_list[0] = &exynos4212_clk_mout_mpll_user.clk;
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_mout_mpll.reg_src.shift = 12;
exynos4_clk_mout_mpll.reg_src.size = 1;
exynos4_clk_aclk_200.sources = &exynos4212_clkset_aclk_200;
exynos4_clk_aclk_200.reg_src.reg = EXYNOS4_CLKSRC_TOP1;
exynos4_clk_aclk_200.reg_src.shift = 20;
exynos4_clk_aclk_200.reg_src.size = 1;
exynos4_clk_fimg2d.enable = exynos4_clk_ip_dmc_ctrl;
exynos4_clk_fimg2d.ctrlbit = (1 << 23);
exynos4_clk_mout_g2d0.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_mout_g2d0.reg_src.shift = 20;
exynos4_clk_mout_g2d0.reg_src.size = 1;
exynos4_clk_mout_g2d1.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_mout_g2d1.reg_src.shift = 24;
exynos4_clk_mout_g2d1.reg_src.size = 1;
exynos4_clk_sclk_fimg2d.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_sclk_fimg2d.reg_src.shift = 28;
exynos4_clk_sclk_fimg2d.reg_src.size = 1;
exynos4_clk_sclk_fimg2d.reg_div.reg = EXYNOS4_CLKDIV_DMC1;
exynos4_clk_sclk_fimg2d.reg_div.shift = 0;
exynos4_clk_sclk_fimg2d.reg_div.size = 4;
exynos4_epll_ops.get_rate = exynos4212_epll_get_rate;
exynos4_epll_ops.set_rate = exynos4212_epll_set_rate;
exynos4_vpll_ops.get_rate = exynos4212_vpll_get_rate;
exynos4_vpll_ops.set_rate = exynos4212_vpll_set_rate;
for (ptr = 0; ptr < ARRAY_SIZE(exynos4212_sysclks); ptr++)
s3c_register_clksrc(exynos4212_sysclks[ptr], 1);
s3c_register_clksrc(exynos4212_clksrcs, ARRAY_SIZE(exynos4212_clksrcs));
s3c_register_clocks(exynos4212_init_clocks, ARRAY_SIZE(exynos4212_init_clocks));
s3c_register_clocks(exynos4212_init_clocks_off, ARRAY_SIZE(exynos4212_init_clocks_off));
s3c_disable_clocks(exynos4212_init_clocks_off, ARRAY_SIZE(exynos4212_init_clocks_off));
s3c_register_clksrc(&exynos4212_clk_isp_srcs_div0, 1);
s3c_register_clksrc(exynos4212_clk_isp_srcs, ARRAY_SIZE(exynos4212_clk_isp_srcs));
s3c_register_clocks(exynos4212_clk_isp, ARRAY_SIZE(exynos4212_clk_isp));
s3c_disable_clocks(&exynos4212_clk_isp_srcs[3].clk, 1);
s3c_disable_clocks(&exynos4212_clk_isp_srcs[4].clk, 1);
s3c_disable_clocks(&exynos4212_clk_isp_srcs[5].clk, 1);
s3c_disable_clocks(&exynos4212_clk_isp_srcs[6].clk, 1);
register_syscore_ops(&exynos4212_clock_syscore_ops);
}
