static int s5p_dp_init_training(struct s5p_dp_device *dp,
			enum link_lane_count_type max_lane,
			enum link_rate_type max_rate)
{
	int retval;

	/*
	 * MACRO_RST must be applied after the PLL_LOCK to avoid
	 * the DP inter pair skew issue for at least 10 us
	 */
	s5p_dp_reset_macro(dp);

	/* Initialize by reading RX's DPCD */
	retval = s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
	if (retval < 0)
		return retval;

	retval = s5p_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
	if (retval < 0)
		return retval;

	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
			dp->link_train.link_rate);
		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
	}

	if (dp->link_train.lane_count == 0) {
		dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
			dp->link_train.lane_count);
		dp->link_train.lane_count = (u8)LANE_COUNT1;
	}

	/* Setup TX lane count & rate */
	if (dp->link_train.lane_count > max_lane)
		dp->link_train.lane_count = max_lane;
	if (dp->link_train.link_rate > max_rate)
		dp->link_train.link_rate = max_rate;

	/* All DP analog module power up */
	s5p_dp_set_analog_power_down(dp, POWER_ALL, 0);

	return 0;
}
Пример #2
0
static int s5p_dp_init_training(struct s5p_dp_device *dp,
			enum link_lane_count_type max_lane,
			enum link_rate_type max_rate)
{
	int retval;
#ifdef CONFIG_S5P_DP_PSR
	u8 data;
#endif
	/*
	 * MACRO_RST must be applied after the PLL_LOCK to avoid
	 * the DP inter pair skew issue for at least 10 us
	 */
	s5p_dp_reset_macro(dp);

#ifdef CONFIG_S5P_DP_PSR
	s5p_dp_enable_rx_to_enhanced_mode(dp, 0);
	s5p_dp_read_byte_from_dpcd(dp,
		DPCD_ADDR_EDP_CONFIGURATION_SET,
			&data);
	s5p_dp_write_byte_to_dpcd(dp,
		DPCD_ADDR_EDP_CONFIGURATION_SET,
		data | (1<<1));
	s5p_dp_enable_enhanced_mode(dp, 1);
#endif

	/* Initialize by reading RX's DPCD */
	retval = s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
	if (retval < 0)
		return retval;

	retval = s5p_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
	if (retval < 0)
		return retval;

	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
			dp->link_train.link_rate);
		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
	}

	if (dp->link_train.lane_count == 0) {
		dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
			dp->link_train.lane_count);
		dp->link_train.lane_count = (u8)LANE_COUNT1;
	}

	/* Setup TX lane count & rate */
	if (dp->link_train.lane_count > max_lane)
		dp->link_train.lane_count = max_lane;
	if (dp->link_train.link_rate > max_rate)
		dp->link_train.link_rate = max_rate;

#ifdef CONFIG_S5P_DP_PSR
	s5p_dp_enable_ssc(dp, 0);
#endif

	/* All DP analog module power up */
	s5p_dp_set_analog_power_down(dp, POWER_ALL, 0);

	return 0;
}