void s5p_i2s_sec_init(void *regs, dma_addr_t phys_base)
{
#ifdef CONFIG_ARCH_S5PV210
/* S5PC110 or S5PV210 */
#define S3C_VA_AUDSS S3C_ADDR(0x01600000) /* Audio SubSystem */
#include <mach/regs-audss.h>
/* We use I2SCLK for rate generation, so set EPLLout as
* the parent of I2SCLK.
*/
u32 val;
val = readl(S5P_CLKSRC_AUDSS);
val &= ~(0x3<<2);
val |= (1<<0);
writel(val, S5P_CLKSRC_AUDSS);
val = readl(S5P_CLKGATE_AUDSS);
val |= (0x7f<<0);
writel(val, S5P_CLKGATE_AUDSS);
#elif defined(CONFIG_ARCH_S5PV310) || defined(CONFIG_ARCH_S5PC210)
u32 val;
#if defined(CONFIG_SND_SOC_SMDK_WM8994_MASTER) || defined(CONFIG_SND_SOC_C1_MC1N2)
/* I2S ratio for Codec master (3+1) = EPLL/4 = 181/4 = 45MHz */
val = 0x300;
#else
/* I2S ratio for AP master (0+1) = EPLL/1 = 181/1 = 181MHz */
val = 0x000;
#endif
/* SRP ratio (15+1)= EPLL/16 = 181/16 = 11MHz
BUS ratio (1+1) = SRP/2 = 11/2 = 5MHz */
val |= 0x01F;
writel(val, S5P_CLKDIV_AUDSS);
writel(0x001, S5P_CLKSRC_AUDSS); /* I2S=Main CLK, ASS=FOUT_EPLL*/
/* CLKGATE should not be controled in here
writel(0x1FF, S5P_CLKGATE_AUDSS);
*/
#else
#error INITIALIZE HERE!
#endif
s5p_i2s0_regs = regs;
s5p_i2s_startup(0);
s5p_snd_txctrl(0);
s5p_idma_init(regs);
}
static int s5p_i2s_wr_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
pr_debug("iis: %s:\n", __func__);
s5p_i2s_do_resume(dai);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
tx_clk_enabled = 1;
else
rx_clk_enabled = 1;
#ifdef CONFIG_S5P_INTERNAL_DMA
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
s5p_i2s_startup(dai);
#endif
return 0;
}
