void up_enable_irq(int irq) { /* This will be called on each interrupt exit whether the interrupt can be * enambled or not. So this assertion is necessarily lame. */ DEBUGASSERT((unsigned)irq < NR_IRQS); /* Check for external interrupt */ if (irq >= SAM_IRQ_INTERRUPT && irq < SAM_IRQ_INTERRUPT + SAM_IRQ_NINTS) { /* Set the appropriate bit in the ISER register to enable the * interrupt */ putreg32((1 << (irq - SAM_IRQ_INTERRUPT)), ARMV6M_NVIC_ISER); } /* Handle processor exceptions. Only SysTick can be disabled */ else if (irq == SAM_IRQ_SYSTICK) { modifyreg32(ARMV6M_SYSTICK_CSR, 0, SYSTICK_CSR_ENABLE); } sam_dumpnvic("enable", irq); }
int up_prioritize_irq(int irq, int priority) { uint32_t regaddr; uint32_t regval; int shift; DEBUGASSERT(irq >= SAM_IRQ_MEMFAULT && irq < SAM_IRQ_NIRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); if (irq < SAM_IRQ_EXTINT) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) */ regaddr = NVIC_SYSH_PRIORITY(irq); irq -= 4; } else { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ irq -= SAM_IRQ_EXTINT; regaddr = NVIC_IRQ_PRIORITY(irq); } regval = getreg32(regaddr); shift = ((irq & 3) << 3); regval &= ~(0xff << shift); regval |= (priority << shift); putreg32(regval, regaddr); sam_dumpnvic("prioritize", irq); return OK; }
void up_enable_irq(int irq) { uintptr_t regaddr; uint32_t regval; uint32_t bit; if (sam_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated * Interrupt Set Enable register. For other exceptions, we need to * set the bit in the System Handler Control and State Register. */ if (irq >= SAM_IRQ_EXTINT) { putreg32(bit, regaddr); } else { regval = getreg32(regaddr); regval |= bit; putreg32(regval, regaddr); } } #ifdef CONFIG_SAM34_GPIO_IRQ else { /* Maybe it is a (derived) GPIO IRQ */ sam_gpioirqenable(irq); } #endif sam_dumpnvic("enable", irq); }
void up_irqinitialize(void) { uint32_t regaddr; int i; /* Disable all interrupts */ putreg32(0xffffffff, ARMV6M_NVIC_ICER); /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR2); putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR3); /* Now set all of the interrupt lines to the default priority */ for (i = 0; i < 8; i++) { regaddr = ARMV6M_NVIC_IPR(i); putreg32(DEFPRIORITY32, regaddr); } /* currents_regs is non-NULL only while processing an interrupt */ CURRENT_REGS = NULL; /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault * under certain conditions. */ irq_attach(SAM_IRQ_SVCALL, up_svcall); irq_attach(SAM_IRQ_HARDFAULT, up_hardfault); /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES irq_attach(SAM_IRQ_NMI, sam_nmi); irq_attach(SAM_IRQ_PENDSV, sam_pendsv); irq_attach(SAM_IRQ_RESERVED, sam_reserved); #endif sam_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS /* And finally, enable interrupts */ up_irq_enable(); #endif }
void up_disable_irq(int irq) { DEBUGASSERT((unsigned)irq < NR_IRQS); /* Check for an external interrupt */ if (irq >= SAM_IRQ_INTERRUPT && irq < SAM_IRQ_INTERRUPT + SAM_IRQ_NINTS) { /* Set the appropriate bit in the ICER register to disable the * interrupt */ putreg32((1 << (irq - SAM_IRQ_INTERRUPT)), ARMV6M_NVIC_ICER); } /* Handle processor exceptions. Only SysTick can be disabled */ else if (irq == SAM_IRQ_SYSTICK) { modifyreg32(ARMV6M_SYSTICK_CSR, SYSTICK_CSR_ENABLE, 0); } sam_dumpnvic("disable", irq); }
void up_irqinitialize(void) { uintptr_t regaddr; #if defined(CONFIG_DEBUG_SYMBOLS) && !defined(CONFIG_ARMV7M_USEBASEPRI) uint32_t regval; #endif int nintlines; int i; /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt * lines that the NVIC supports, defined in groups of 32. That is, * the total number of interrupt lines is up to (32*(INTLINESNUM+1)). * * 0 -> 32 interrupt lines, 1 enable register, 8 priority registers * 1 -> 64 " " " ", 2 enable registers, 16 priority registers * 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers * ... */ nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1; /* Disable all interrupts. There are nintlines interrupt enable * registers. */ for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; i > 0; i--, regaddr += 4) { putreg32(0, regaddr); } /* Colorize the interrupt stack for debug purposes */ #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 { size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size), intstack_size); } #endif /* Make sure that we are using the correct vector table. The default * vector address is 0x0000:0000 but if we are executing code that is * positioned in SRAM or in external FLASH, then we may need to reset * the interrupt vector so that it refers to the table in SRAM or in * external FLASH. */ putreg32((uint32_t)_vectors, NVIC_VECTAB); #ifdef CONFIG_ARCH_RAMVECTORS /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based * vector table that requires special initialization. */ up_ramvec_initialize(); #endif /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); /* Now set all of the interrupt lines to the default priority. There are * nintlines * 8 priority registers. */ for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY; i > 0; i--, regaddr += 4) { putreg32(DEFPRIORITY32, regaddr); } /* currents_regs is non-NULL only while processing an interrupt */ current_regs = NULL; /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault * under certain conditions. */ irq_attach(SAM_IRQ_SVCALL, up_svcall); irq_attach(SAM_IRQ_HARDFAULT, up_hardfault); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(SAM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI sam_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. */ #ifdef CONFIG_ARMV7M_MPU irq_attach(SAM_IRQ_MEMFAULT, up_memfault); up_enable_irq(SAM_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG irq_attach(SAM_IRQ_NMI, sam_nmi); #ifndef CONFIG_ARMV7M_MPU irq_attach(SAM_IRQ_MEMFAULT, up_memfault); #endif irq_attach(SAM_IRQ_BUSFAULT, sam_busfault); irq_attach(SAM_IRQ_USAGEFAULT, sam_usagefault); irq_attach(SAM_IRQ_PENDSV, sam_pendsv); irq_attach(SAM_IRQ_DBGMONITOR, sam_dbgmonitor); irq_attach(SAM_IRQ_RESERVED, sam_reserved); #endif sam_dumpnvic("initial", SAM_IRQ_NIRQS); /* If a debugger is connected, try to prevent it from catching hardfaults. * If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal * operation. */ #if defined(CONFIG_DEBUG_SYMBOLS) && !defined(CONFIG_ARMV7M_USEBASEPRI) regval = getreg32(NVIC_DEMCR); regval &= ~NVIC_DEMCR_VCHARDERR; putreg32(regval, NVIC_DEMCR); #endif #ifndef CONFIG_SUPPRESS_INTERRUPTS /* Initialize logic to support a second level of interrupt decoding for * GPIO pins. */ #ifdef CONFIG_SAM34_GPIO_IRQ sam_gpioirqinitialize(); #endif /* And finally, enable interrupts */ irqenable(); #endif }