static int rtc_suspend(struct amba_device *dev, u32 state)
{
struct timespec rtc;
rtc.tv_sec = readl(rtc_base + RTC_DR);
rtc.tv_nsec = 0;
save_time_delta(&rtc_delta, &rtc);
return 0;
}
static int AMI8563_rtc_suspend(struct i2c_client * client, pm_message_t mesg)
{
struct rtc_time tm;
struct timespec time;
memset(&time, 0, sizeof(struct timespec));
AMI8563_get_datetime(client, &tm);
rtc_tm_to_time(&tm, &time.tv_sec);
save_time_delta(&ami8563_rtc_delta, &time);
return 0;
}
/*!
***********************************************************************
* -Function:
* imap_rtc_suspend
* imap_rtc_resume
*
* -Description:
* RTC PM functions, RTC should be disabled before suspend, and re-enabled
* after resuem. Alarm state should be leave alone.
*
* -Input Param
* pdev platform device pointer provided by system
* state Standard function interface required, but not used here
*
* -Output Param
* None
*
* -Return
* 0 On success
*
* -Others
* None
***********************************************************************
*/
static int imap_rtc_suspend(struct platform_device *pdev, pm_message_t state)
{
struct rtc_time tm;
struct timespec time;
time.tv_nsec = 0;
/* save TICNT for anyone using periodic interrupts */
ticnt_save = readb(imap_rtc_base + IMAPX200_TICNT);
imap_rtc_gettime(&pdev->dev, &tm);
rtc_tm_to_time(&tm, &time.tv_sec);
save_time_delta(&imap_rtc_delta, &time);
return 0;
}
static int s3c_rtc_suspend(struct platform_device *pdev, pm_message_t state)
{
struct rtc_time tm;
struct timespec time;
time.tv_nsec = 0;
/* save TICNT for anyone using periodic interrupts */
ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
/* calculate time delta for suspend */
s3c_rtc_gettime(&pdev->dev, &tm);
rtc_tm_to_time(&tm, &time.tv_sec);
save_time_delta(&s3c_rtc_delta, &time);
s3c_rtc_enable(pdev, 0);
return 0;
}
static int lpc22xx_rtc_suspend(struct platform_device *pdev, pm_message_t state)
{
struct rtc_time tm;
struct timespec time;
time.tv_nsec = 0;
/* calculate time delta for suspend */
lpc22xx_rtc_readtime(&pdev->dev, &tm);
rtc_tm_to_time(&tm, &time.tv_sec);
save_time_delta(&lpc22xx_rtc_delta, &time);
if((REG_RTC_CIIR & 0xFF)||
((REG_RTC_AMR & 0xFF)!=0xFF)||
(REG_RTC_CISS & 0x80)) {
if (device_may_wakeup(&pdev->dev))
enable_irq_wake(LPC22xx_INTERRUPT_RTC);
}
return 0;
}
static int omap_rtc_suspend(struct platform_device *pdev, pm_message_t state)
{
struct rtc_time rtc_tm;
struct timespec time;
time.tv_nsec = 0;
omap_rtc_read_time(NULL, &rtc_tm);
rtc_tm_to_time(&rtc_tm, &time.tv_sec);
save_time_delta(&rtc_delta, &time);
irqstat = rtc_read(OMAP_RTC_INTERRUPTS_REG);
/* FIXME the RTC alarm is not currently acting as a wakeup event
* source, and in fact this enable() call is just saving a flag
* that's never used...
*/
if (device_may_wakeup(&pdev->dev))
enable_irq_wake(omap_rtc_alarm);
else
rtc_write(0, OMAP_RTC_INTERRUPTS_REG);
return 0;
}
static int __devinit s3c_rtc_probe(struct platform_device *pdev)
{
struct rtc_device *rtc;
struct resource *res;
unsigned char bcd_tmp,bcd_loop;
int ret;
#ifdef CONFIG_RTC_DRV_MAX8998
struct rtc_time tm;
#endif
pr_debug("%s: probe=%p\n", __func__, pdev);
/* find the IRQs */
s3c_rtc_tickno = platform_get_irq(pdev, 1);
if (s3c_rtc_tickno < 0) {
dev_err(&pdev->dev, "no irq for rtc tick\n");
return -ENOENT;
}
s3c_rtc_alarmno = platform_get_irq(pdev, 0);
if (s3c_rtc_alarmno < 0) {
dev_err(&pdev->dev, "no irq for alarm\n");
return -ENOENT;
}
pr_debug("s3c2410_rtc: tick irq %d, alarm irq %d\n",
s3c_rtc_tickno, s3c_rtc_alarmno);
/* get the memory region */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
dev_err(&pdev->dev, "failed to get memory region resource\n");
return -ENOENT;
}
s3c_rtc_mem = request_mem_region(res->start,
res->end-res->start+1,
pdev->name);
if (s3c_rtc_mem == NULL) {
dev_err(&pdev->dev, "failed to reserve memory region\n");
ret = -ENOENT;
goto err_nores;
}
s3c_rtc_base = ioremap(res->start, res->end - res->start + 1);
if (s3c_rtc_base == NULL) {
dev_err(&pdev->dev, "failed ioremap()\n");
ret = -EINVAL;
goto err_nomap;
}
/* check to see if everything is setup correctly */
s3c_rtc_enable(pdev, 1);
pr_debug("s3c2410_rtc: RTCCON=%02x\n",
readb(s3c_rtc_base + S3C2410_RTCCON));
s3c_rtc_setfreq(&pdev->dev, 1);
device_init_wakeup(&pdev->dev, 1);
#ifdef CONFIG_RTC_DRV_MAX8998
max8998_rtc_read_time(&tm);
#endif
/* register RTC and exit */
rtc = rtc_device_register("s3c", &pdev->dev, &s3c_rtcops,
THIS_MODULE);
if (IS_ERR(rtc)) {
dev_err(&pdev->dev, "cannot attach rtc\n");
ret = PTR_ERR(rtc);
goto err_nortc;
}
rtc->max_user_freq = S3C_MAX_CNT;
#ifdef CONFIG_RTC_DRV_MAX8998
s3c_rtc_settime(rtc, &tm); //update from pmic
#endif
#ifdef SET_RTC_DEFAULT_RESET_TIME
{
struct rtc_time tm;
s3c_rtc_gettime (pdev, &tm);
if (rtc_valid_tm (&tm) != 0)
{
struct rtc_time reset_tm = {
.tm_sec = DEFAULT_RESET_TIME_SEC,
.tm_min = DEFAULT_RESET_TIME_MIN,
.tm_hour = DEFAULT_RESET_TIME_HOUR,
.tm_mday = DEFAULT_RESET_TIME_DATE,
.tm_mon = DEFAULT_RESET_TIME_MON - 1,
.tm_year = DEFAULT_RESET_TIME_YEAR - 1900,
};
s3c_rtc_settime (pdev, &reset_tm);
#ifdef CONFIG_RTC_DRV_MAX8998
max8998_rtc_set_time(&reset_tm); // also update pmic rtc as default
#endif
}
}
#else
/* check rtc time */
for (bcd_loop = S3C2410_RTCSEC ; bcd_loop <= S3C2410_RTCYEAR ; bcd_loop +=0x4)
{
bcd_tmp = readb(s3c_rtc_base + bcd_loop);
if(((bcd_tmp & 0xf) > 0x9) || ((bcd_tmp & 0xf0) > 0x90))
writeb(0, s3c_rtc_base + bcd_loop);
}
#endif /* SET_RTC_DEFAULT_RESET_TIME */
platform_set_drvdata(pdev, rtc);
#ifdef CONFIG_RTC_S3C_SYNC_SYSTEM_TIME
rtc_sync_start_save_delta();
#endif /* CONFIG_RTC_S3C_SYNC_SYSTEM_TIME */
return 0;
err_nortc:
s3c_rtc_enable(pdev, 0);
iounmap(s3c_rtc_base);
err_nomap:
release_resource(s3c_rtc_mem);
err_nores:
return ret;
}
#ifdef CONFIG_PM
/* RTC Power management control */
static struct timespec s3c_rtc_delta;
static int ticnt_save;
static int s3c_rtc_suspend(struct platform_device *pdev, pm_message_t state)
{
struct rtc_time tm;
struct timespec time;
time.tv_nsec = 0;
/* save TICNT for anyone using periodic interrupts */
ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
s3c_rtc_gettime(&pdev->dev, &tm);
rtc_tm_to_time(&tm, &time.tv_sec);
save_time_delta(&s3c_rtc_delta, &time);
if (gpio_get_value(GPIO_WLAN_BT_EN) == 0) /* BCM4329 isnt working */
s3c_rtc_enable(pdev, 0);
#ifdef CONFIG_RTC_S3C_SYNC_SYSTEM_TIME
cancel_delayed_work(&rtc_sync_work);
#endif /* CONFIG_RTC_S3C_SYNC_SYSTEM_TIME */
return 0;
}
static int s3c_rtc_resume(struct platform_device *pdev)
{
struct rtc_time tm;
struct timespec time;
time.tv_nsec = 0;
if (gpio_get_value(GPIO_WLAN_BT_EN) == 0) /* BCM4329 isnt working */
s3c_rtc_enable(pdev, 1);
s3c_rtc_gettime(&pdev->dev, &tm);
rtc_tm_to_time(&tm, &time.tv_sec);
restore_time_delta(&s3c_rtc_delta, &time);
writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
#ifdef CONFIG_RTC_S3C_SYNC_SYSTEM_TIME
rtc_sync_start ();
#endif
return 0;
}
#else
#define s3c_rtc_suspend NULL
#define s3c_rtc_resume NULL
#endif
static struct platform_driver s3c2410_rtc_driver = {
.probe = s3c_rtc_probe,
.remove = __devexit_p(s3c_rtc_remove),
.suspend = s3c_rtc_suspend,
.resume = s3c_rtc_resume,
.driver = {
.name = "s3c2410-rtc",
.owner = THIS_MODULE,
},
};
static char __initdata banner[] = "S3C24XX RTC, (c) 2004,2006 Simtec Electronics\n";
static int __init s3c_rtc_init(void)
{
printk(banner);
return platform_driver_register(&s3c2410_rtc_driver);
}
static int sa11x0_pm_enter(suspend_state_t state)
{
unsigned long gpio, sleep_save[SLEEP_SAVE_SIZE];
struct timespec delta, rtc;
/* preserve current time */
rtc.tv_sec = RCNR;
rtc.tv_nsec = 0;
save_time_delta(&delta, &rtc);
gpio = GPLR;
/* save vital registers */
SAVE(GPDR);
SAVE(GAFR);
SAVE(PPDR);
SAVE(PPSR);
SAVE(PPAR);
SAVE(PSDR);
SAVE(Ser1SDCR0);
/* Clear previous reset status */
RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
/* set resume return address */
PSPR = virt_to_phys(sa1100_cpu_resume);
/* go zzz */
sa1100_cpu_suspend();
cpu_init();
/*
* Ensure not to come back here if it wasn't intended
*/
PSPR = 0;
/*
* Ensure interrupt sources are disabled; we will re-init
* the interrupt subsystem via the device manager.
*/
ICLR = 0;
ICCR = 1;
ICMR = 0;
/* restore registers */
RESTORE(GPDR);
RESTORE(GAFR);
RESTORE(PPDR);
RESTORE(PPSR);
RESTORE(PPAR);
RESTORE(PSDR);
RESTORE(Ser1SDCR0);
GPSR = gpio;
GPCR = ~gpio;
/*
* Clear the peripheral sleep-hold bit.
*/
PSSR = PSSR_PH;
/* restore current time */
rtc.tv_sec = RCNR;
restore_time_delta(&delta, &rtc);
return 0;
}
int pxa_pm_enter(suspend_state_t state)
{
unsigned long sleep_save[SLEEP_SAVE_SIZE];
unsigned long checksum = 0;
struct timespec delta, rtc;
int i;
extern void pxa_cpu_pm_enter(suspend_state_t state);
#ifdef CONFIG_IWMMXT
/* force any iWMMXt context to ram **/
iwmmxt_task_disable(NULL);
#endif
/* preserve current time */
rtc.tv_sec = RCNR;
rtc.tv_nsec = 0;
save_time_delta(&delta, &rtc);
SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
SAVE(GAFR0_L); SAVE(GAFR0_U);
SAVE(GAFR1_L); SAVE(GAFR1_U);
SAVE(GAFR2_L); SAVE(GAFR2_U);
#ifdef CONFIG_PXA27x
SAVE(MDREFR);
SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3);
SAVE(GAFR3_L); SAVE(GAFR3_U);
SAVE(PWER); SAVE(PCFR); SAVE(PRER);
SAVE(PFER); SAVE(PKWR);
#endif
SAVE(ICMR);
ICMR = 0;
SAVE(CKEN);
SAVE(PSTR);
/* Note: wake up source are set up in each machine specific files */
/* clear GPIO transition detect bits */
GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
#ifdef CONFIG_PXA27x
GEDR3 = GEDR3;
#endif
/* Clear sleep reset status */
RCSR = RCSR_SMR;
/* before sleeping, calculate and save a checksum */
for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
checksum += sleep_save[i];
sleep_save[SLEEP_SAVE_CKSUM] = checksum;
/* *** go zzz *** */
pxa_cpu_pm_enter(state);
cpu_init();
/* after sleeping, validate the checksum */
checksum = 0;
for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
checksum += sleep_save[i];
/* if invalid, display message and wait for a hardware reset */
if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) {
#ifdef CONFIG_ARCH_LUBBOCK
LUB_HEXLED = 0xbadbadc5;
#endif
while (1)
pxa_cpu_pm_enter(state);
}
/* ensure not to come back here if it wasn't intended */
PSPR = 0;
/* restore registers */
RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
RESTORE(GAFR0_L); RESTORE(GAFR0_U);
RESTORE(GAFR1_L); RESTORE(GAFR1_U);
RESTORE(GAFR2_L); RESTORE(GAFR2_U);
RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
#ifdef CONFIG_PXA27x
RESTORE(MDREFR);
RESTORE_GPLEVEL(3); RESTORE(GPDR3);
RESTORE(GAFR3_L); RESTORE(GAFR3_U);
RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3);
RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
RESTORE(PFER); RESTORE(PKWR);
#endif
PSSR = PSSR_RDH | PSSR_PH;
RESTORE(CKEN);
ICLR = 0;
ICCR = 1;
RESTORE(ICMR);
RESTORE(PSTR);
/* restore current time */
rtc.tv_sec = RCNR;
restore_time_delta(&delta, &rtc);
#ifdef DEBUG
printk(KERN_DEBUG "*** made it back from resume\n");
#endif
return 0;
}
