/** * @brief South Bridge CIMx romstage entry, * wrapper of sbPowerOnInit entry point. */ void sb_Poweron_Init(void) { AMDSBCFG sb_early_cfg; printk(BIOS_SPEW, "cimx/sb700 early.c, %s() Start:\n", __func__); /* Enable A-Link Base Address */ //sb_enable_alink (); sb700_cimx_config(&sb_early_cfg); sbPowerOnInit(&sb_early_cfg); printk(BIOS_SPEW, "cimx/sb700 early.c, %s() End\n", __func__); }
static void sb700_enable(device_t dev) { struct southbridge_amd_cimx_sb700_config *sb_chip = (struct southbridge_amd_cimx_sb700_config *)(dev->chip_info); printk(BIOS_DEBUG, "sb700_enable() "); switch (dev->path.pci.devfn) { case (0x11 << 3) | 0: /* 0:11.0 SATA */ sb700_cimx_config(sb_config); if (dev->enabled) { sb_config->SataController = CIMX_OPTION_ENABLED; if (1 == sb_chip->boot_switch_sata_ide) sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. else if (0 == sb_chip->boot_switch_sata_ide) sb_config->SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. } else { sb_config->SataController = CIMX_OPTION_DISABLED; } break; case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ break; case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ { u32 ioapic_base; printk(BIOS_DEBUG, "sm_init().\n"); ioapic_base = IO_APIC_ADDR; clear_ioapic(ioapic_base); /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ if (CONFIG_MAX_CPUS >= 16) setup_ioapic(ioapic_base, 0); else setup_ioapic(ioapic_base, CONFIG_MAX_CPUS + 1); } break; case (0x14 << 3) | 1: /* 0:14:1 IDE */ break; case (0x14 << 3) | 2: /* 0:14:2 HDA */ if (dev->enabled) { if (AZALIA_DISABLE == sb_config->AzaliaController) { sb_config->AzaliaController = AZALIA_AUTO; } printk(BIOS_DEBUG, "hda enabled\n"); } else { sb_config->AzaliaController = AZALIA_DISABLE; printk(BIOS_DEBUG, "hda disabled\n"); } break; case (0x14 << 3) | 3: /* 0:14:3 LPC */ break; case (0x14 << 3) | 4: /* 0:14:4 PCI */ break; case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ /* call CIMX entry after last device enable */ sb_Before_Pci_Init(); break; default: break; } }