static int c101_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) { const size_t size = sizeof(sync_serial_settings); sync_serial_settings new_line; sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; port_t *port = dev_to_port(dev); #ifdef DEBUG_RINGS if (cmd == SIOCDEVPRIVATE) { sca_dump_rings(dev); printk(KERN_DEBUG "MSCI1: ST: %02x %02x %02x %02x\n", sca_in(MSCI1_OFFSET + ST0, port), sca_in(MSCI1_OFFSET + ST1, port), sca_in(MSCI1_OFFSET + ST2, port), sca_in(MSCI1_OFFSET + ST3, port)); return 0; } #endif if (cmd != SIOCWANDEV) return hdlc_ioctl(dev, ifr, cmd); switch(ifr->ifr_settings.type) { case IF_GET_IFACE: ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; if (ifr->ifr_settings.size < size) { ifr->ifr_settings.size = size; /* data size wanted */ return -ENOBUFS; } if (copy_to_user(line, &port->settings, size)) return -EFAULT; return 0; case IF_IFACE_SYNC_SERIAL: if(!capable(CAP_NET_ADMIN)) return -EPERM; if (copy_from_user(&new_line, line, size)) return -EFAULT; if (new_line.clock_type != CLOCK_EXT && new_line.clock_type != CLOCK_TXFROMRX && new_line.clock_type != CLOCK_INT && new_line.clock_type != CLOCK_TXINT) return -EINVAL; /* No such clock setting */ if (new_line.loopback != 0 && new_line.loopback != 1) return -EINVAL; memcpy(&port->settings, &new_line, size); /* Update settings */ c101_set_iface(port); return 0; default: return hdlc_ioctl(dev, ifr, cmd); } }
/* Transmit DMA service */ static inline void sca_tx_done(port_t *port) { struct net_device *dev = port->netdev; card_t* card = port->card; u8 stat; spin_lock(&port->lock); stat = sca_in(DSR_TX(port->chan), card); /* read DMA Status */ /* Reset DSR status bits */ sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, DSR_TX(port->chan), card); while (1) { pkt_desc __iomem *desc = desc_address(port, port->txlast, 1); u8 stat = readb(&desc->stat); if (!(stat & ST_TX_OWNRSHP)) break; /* not yet transmitted */ if (stat & ST_TX_UNDRRUN) { dev->stats.tx_errors++; dev->stats.tx_fifo_errors++; } else { dev->stats.tx_packets++; dev->stats.tx_bytes += readw(&desc->len); } writeb(0, &desc->stat); /* Free descriptor */ port->txlast = (port->txlast + 1) % card->tx_ring_buffers; } netif_wake_queue(dev); spin_unlock(&port->lock); }
/* Transmit DMA interrupt service */ static inline void sca_tx_intr(port_t *port) { struct net_device *dev = port_to_dev(port); u16 dmac = get_dmac_tx(port); card_t* card = port_to_card(port); u8 stat; spin_lock(&port->lock); stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */ /* Reset DSR status bits */ sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, DSR_TX(phy_node(port)), card); while (1) { pkt_desc __iomem *desc; u32 desc_off = desc_offset(port, port->txlast, 1); u32 cda = sca_inw(dmac + CDAL, card); if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) break; /* Transmitter is/will_be sending this frame */ desc = desc_address(port, port->txlast, 1); dev->stats.tx_packets++; dev->stats.tx_bytes += readw(&desc->len); writeb(0, &desc->stat); /* Free descriptor */ port->txlast = next_desc(port, port->txlast, 1); } netif_wake_queue(dev); spin_unlock(&port->lock); }
static inline void set_carrier(port_t *port) { if (!(sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD)) netif_carrier_on(port_to_dev(port)); else netif_carrier_off(port_to_dev(port)); }
static void sca_set_port(port_t *port) { card_t* card = port_to_card(port); u16 msci = get_msci(port); u8 md2 = sca_in(msci + MD2, card); unsigned int tmc, br = 10, brv = 1024; if (port->settings.clock_rate > 0) { /* Try lower br for better accuracy*/ do { br--; brv >>= 1; /* brv = 2^9 = 512 max in specs */ /* Baud Rate = CLOCK_BASE / TMC / 2^BR */ tmc = CLOCK_BASE / brv / port->settings.clock_rate; }while (br > 1 && tmc <= 128); if (tmc < 1) { tmc = 1; br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */ brv = 1; } else if (tmc > 255) tmc = 256; /* tmc=0 means 256 - low baud rates */ port->settings.clock_rate = CLOCK_BASE / brv / tmc; } else {
static void sca_set_port(port_t *port) { card_t* card = port_to_card(port); u16 msci = get_msci(port); u8 md2 = sca_in(msci + MD2, card); unsigned int tmc, br = 10, brv = 1024; if (port->settings.clock_rate > 0) { do { br--; brv >>= 1; tmc = CLOCK_BASE / brv / port->settings.clock_rate; } while (br > 1 && tmc <= 128); if (tmc < 1) { tmc = 1; br = 0; brv = 1; } else if (tmc > 255) tmc = 256; port->settings.clock_rate = CLOCK_BASE / brv / tmc; } else {
/* MSCI interrupt service */ static inline void sca_msci_intr(port_t *port) { u16 msci = get_msci(port); card_t* card = port_to_card(port); u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */ /* Reset MSCI TX underrun and CDCD status bit */ sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card); if (stat & ST1_UDRN) { struct net_device_stats *stats = hdlc_stats(port_to_dev(port)); stats->tx_errors++; /* TX Underrun error detected */ stats->tx_fifo_errors++; } if (stat & ST1_CDCD) hdlc_set_carrier(!(sca_in(msci + ST3, card) & ST3_DCD), port_to_dev(port)); }
static void sca_msci_intr(port_t *port) { u8 stat = sca_in(MSCI0_OFFSET + ST1, port); /* read MSCI ST1 status */ /* Reset MSCI TX underrun and CDCD (ignored) status bit */ sca_out(stat & (ST1_UDRN | ST1_CDCD), MSCI0_OFFSET + ST1, port); if (stat & ST1_UDRN) { /* TX Underrun error detected */ port_to_dev(port)->stats.tx_errors++; port_to_dev(port)->stats.tx_fifo_errors++; } stat = sca_in(MSCI1_OFFSET + ST1, port); /* read MSCI1 ST1 status */ /* Reset MSCI CDCD status bit - uses ch#2 DCD input */ sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, port); if (stat & ST1_CDCD) set_carrier(port); }
/* MSCI interrupt service */ static inline void sca_msci_intr(port_t *port) { u16 msci = get_msci(port); card_t* card = port->card; if (sca_in(msci + ST1, card) & ST1_CDCD) { /* Reset MSCI CDCD status bit */ sca_out(ST1_CDCD, msci + ST1, card); sca_set_carrier(port); } }
/* Receive DMA service */ static inline int sca_rx_done(port_t *port, int budget) { struct net_device *dev = port->netdev; u16 dmac = get_dmac_rx(port); card_t *card = port->card; u8 stat = sca_in(DSR_RX(port->chan), card); /* read DMA Status */ int received = 0; /* Reset DSR status bits */ sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, DSR_RX(port->chan), card); if (stat & DSR_BOF) /* Dropped one or more frames */ dev->stats.rx_over_errors++; while (received < budget) { u32 desc_off = hd_desc_offset(port, port->rxin, 0); pkt_desc __iomem *desc; u32 cda = sca_inl(dmac + CDAL, card); if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) break; /* No frame received */ desc = desc_address(port, port->rxin, 0); stat = readb(&desc->stat); if (!(stat & ST_RX_EOM)) port->rxpart = 1; /* partial frame received */ else if ((stat & ST_ERROR_MASK) || port->rxpart) { dev->stats.rx_errors++; if (stat & ST_RX_OVERRUN) dev->stats.rx_fifo_errors++; else if ((stat & (ST_RX_SHORT | ST_RX_ABORT | ST_RX_RESBIT)) || port->rxpart) dev->stats.rx_frame_errors++; else if (stat & ST_RX_CRC) dev->stats.rx_crc_errors++; if (stat & ST_RX_EOM) port->rxpart = 0; /* received last fragment */ } else { sca_rx(card, port, desc, port->rxin); received++; } /* Set new error descriptor address */ sca_outl(desc_off, dmac + EDAL, card); port->rxin = (port->rxin + 1) % card->rx_ring_buffers; } /* make sure RX DMA is enabled */ sca_out(DSR_DE, DSR_RX(port->chan), card); return received; }
static inline int sca_intr_status(card_t *card) { u8 result = 0; u8 isr0 = sca_in(ISR0, card); u8 isr1 = sca_in(ISR1, card); if (isr1 & 0x03) result |= SCA_INTR_DMAC_RX(0); if (isr1 & 0x0C) result |= SCA_INTR_DMAC_TX(0); if (isr1 & 0x30) result |= SCA_INTR_DMAC_RX(1); if (isr1 & 0xC0) result |= SCA_INTR_DMAC_TX(1); if (isr0 & 0x0F) result |= SCA_INTR_MSCI(0); if (isr0 & 0xF0) result |= SCA_INTR_MSCI(1); if (!(result & SCA_INTR_DMAC_TX(0))) if (sca_in(DSR_TX(0), card) & DSR_EOM) result |= SCA_INTR_DMAC_TX(0); if (!(result & SCA_INTR_DMAC_TX(1))) if (sca_in(DSR_TX(1), card) & DSR_EOM) result |= SCA_INTR_DMAC_TX(1); return result; }
/* Receive DMA interrupt service */ static inline void sca_rx_intr(port_t *port) { struct net_device *dev = port_to_dev(port); u16 dmac = get_dmac_rx(port); card_t *card = port_to_card(port); u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */ /* Reset DSR status bits */ sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, DSR_RX(phy_node(port)), card); if (stat & DSR_BOF) /* Dropped one or more frames */ dev->stats.rx_over_errors++; while (1) { u32 desc_off = desc_offset(port, port->rxin, 0); pkt_desc __iomem *desc; u32 cda = sca_inw(dmac + CDAL, card); if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) break; /* No frame received */ desc = desc_address(port, port->rxin, 0); stat = readb(&desc->stat); if (!(stat & ST_RX_EOM)) port->rxpart = 1; /* partial frame received */ else if ((stat & ST_ERROR_MASK) || port->rxpart) { dev->stats.rx_errors++; if (stat & ST_RX_OVERRUN) dev->stats.rx_fifo_errors++; else if ((stat & (ST_RX_SHORT | ST_RX_ABORT | ST_RX_RESBIT)) || port->rxpart) dev->stats.rx_frame_errors++; else if (stat & ST_RX_CRC) dev->stats.rx_crc_errors++; if (stat & ST_RX_EOM) port->rxpart = 0; /* received last fragment */ } else sca_rx(card, port, desc, port->rxin); /* Set new error descriptor address */ sca_outw(desc_off, dmac + EDAL, card); port->rxin = next_desc(port, port->rxin, 0); } /* make sure RX DMA is enabled */ sca_out(DSR_DE, DSR_RX(phy_node(port)), card); }
static inline void sca_rx_intr(port_t *port) { struct net_device *dev = port_to_dev(port); u16 dmac = get_dmac_rx(port); card_t *card = port_to_card(port); u8 stat = sca_in(DSR_RX(phy_node(port)), card); sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, DSR_RX(phy_node(port)), card); if (stat & DSR_BOF) dev->stats.rx_over_errors++; while (1) { u32 desc_off = desc_offset(port, port->rxin, 0); pkt_desc __iomem *desc; u32 cda = sca_inw(dmac + CDAL, card); if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) break; desc = desc_address(port, port->rxin, 0); stat = readb(&desc->stat); if (!(stat & ST_RX_EOM)) port->rxpart = 1; else if ((stat & ST_ERROR_MASK) || port->rxpart) { dev->stats.rx_errors++; if (stat & ST_RX_OVERRUN) dev->stats.rx_fifo_errors++; else if ((stat & (ST_RX_SHORT | ST_RX_ABORT | ST_RX_RESBIT)) || port->rxpart) dev->stats.rx_frame_errors++; else if (stat & ST_RX_CRC) dev->stats.rx_crc_errors++; if (stat & ST_RX_EOM) port->rxpart = 0; } else sca_rx(card, port, desc, port->rxin); sca_outw(desc_off, dmac + EDAL, card); port->rxin = next_desc(port, port->rxin, 0); } sca_out(DSR_DE, DSR_RX(phy_node(port)), card); }
static inline int sca_intr_status(card_t *card) { u8 result = 0; #ifdef __HD64570_H /* HD64570 */ u8 isr0 = sca_in(ISR0, card); u8 isr1 = sca_in(ISR1, card); if (isr1 & 0x03) result |= SCA_INTR_DMAC_RX(0); if (isr1 & 0x0C) result |= SCA_INTR_DMAC_TX(0); if (isr1 & 0x30) result |= SCA_INTR_DMAC_RX(1); if (isr1 & 0xC0) result |= SCA_INTR_DMAC_TX(1); if (isr0 & 0x0F) result |= SCA_INTR_MSCI(0); if (isr0 & 0xF0) result |= SCA_INTR_MSCI(1); #else /* HD64572 */ u32 isr0 = sca_inl(ISR0, card); if (isr0 & 0x0000000F) result |= SCA_INTR_DMAC_RX(0); if (isr0 & 0x000000F0) result |= SCA_INTR_DMAC_TX(0); if (isr0 & 0x00000F00) result |= SCA_INTR_DMAC_RX(1); if (isr0 & 0x0000F000) result |= SCA_INTR_DMAC_TX(1); if (isr0 & 0x003E0000) result |= SCA_INTR_MSCI(0); if (isr0 & 0x3E000000) result |= SCA_INTR_MSCI(1); #endif /* HD64570 vs HD64572 */ if (!(result & SCA_INTR_DMAC_TX(0))) if (sca_in(DSR_TX(0), card) & DSR_EOM) result |= SCA_INTR_DMAC_TX(0); if (!(result & SCA_INTR_DMAC_TX(1))) if (sca_in(DSR_TX(1), card) & DSR_EOM) result |= SCA_INTR_DMAC_TX(1); return result; }
static inline void sca_set_carrier(port_t *port) { if (!(sca_in(get_msci(port) + ST3, port_to_card(port)) & ST3_DCD)) { #ifdef DEBUG_LINK printk(KERN_DEBUG "%s: sca_set_carrier on\n", port_to_dev(port)->name); #endif netif_carrier_on(port_to_dev(port)); } else { #ifdef DEBUG_LINK printk(KERN_DEBUG "%s: sca_set_carrier off\n", port_to_dev(port)->name); #endif netif_carrier_off(port_to_dev(port)); } }
static inline void sca_msci_intr(port_t *port) { u16 msci = get_msci(port); card_t* card = port_to_card(port); u8 stat = sca_in(msci + ST1, card); sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card); if (stat & ST1_UDRN) { port_to_dev(port)->stats.tx_errors++; port_to_dev(port)->stats.tx_fifo_errors++; } if (stat & ST1_CDCD) sca_set_carrier(port); }
/* MSCI interrupt service */ static inline void sca_msci_intr(port_t *port) { u16 msci = get_msci(port); card_t* card = port_to_card(port); u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */ /* Reset MSCI TX underrun and CDCD status bit */ sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card); if (stat & ST1_UDRN) { /* TX Underrun error detected */ port_to_dev(port)->stats.tx_errors++; port_to_dev(port)->stats.tx_fifo_errors++; } if (stat & ST1_CDCD) sca_set_carrier(port); }
static void sca_init_sync_port(port_t *port) { card_t *card = port_to_card(port); int transmit, i; port->rxin = 0; port->txin = 0; port->txlast = 0; #if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED) openwin(card, 0); #endif for (transmit = 0; transmit < 2; transmit++) { u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port); u16 buffs = transmit ? card->tx_ring_buffers : card->rx_ring_buffers; for (i = 0; i < buffs; i++) { pkt_desc __iomem *desc = desc_address(port, i, transmit); u16 chain_off = desc_offset(port, i + 1, transmit); u32 buff_off = buffer_offset(port, i, transmit); writea(chain_off, &desc->cp); writel(buff_off, &desc->bp); writew(0, &desc->len); writeb(0, &desc->stat); } /* DMA disable - to halt state */ sca_out(0, transmit ? DSR_TX(phy_node(port)) : DSR_RX(phy_node(port)), card); /* software ABORT - to initial state */ sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) : DCR_RX(phy_node(port)), card); #ifdef __HD64570_H sca_out(0, dmac + CPB, card); /* pointer base */ #endif /* current desc addr */ sca_outa(desc_offset(port, 0, transmit), dmac + CDAL, card); if (!transmit) sca_outa(desc_offset(port, buffs - 1, transmit), dmac + EDAL, card); else sca_outa(desc_offset(port, 0, transmit), dmac + EDAL, card); /* clear frame end interrupt counter */ sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) : DCR_RX(phy_node(port)), card); if (!transmit) { /* Receive */ /* set buffer length */ sca_outw(HDLC_MAX_MRU, dmac + BFLL, card); /* Chain mode, Multi-frame */ sca_out(0x14, DMR_RX(phy_node(port)), card); sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)), card); /* DMA enable */ sca_out(DSR_DE, DSR_RX(phy_node(port)), card); } else { /* Transmit */ /* Chain mode, Multi-frame */ sca_out(0x14, DMR_TX(phy_node(port)), card); /* enable underflow interrupts */ sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card); } } hdlc_set_carrier(!(sca_in(get_msci(port) + ST3, card) & ST3_DCD), port_to_dev(port)); }