/**
* \brief Waits the TOKEN which notify the end of write block transfer
*
* \return true if success, otherwise false
* with a update of \ref sd_mmc_spi_err.
*/
static bool sd_mmc_spi_stop_write_block(void)
{
uint8_t resp;
uint16_t crc;
// Send CRC
crc = 0xFFFF; /// CRC is disabled in SPI mode
sspi_write_packet((uint8_t *)&crc, 2);
// Receive data response token
sspi_read_packet(&resp, 1);
if (!SPI_TOKEN_DATA_RESP_VALID(resp)) {
sd_mmc_spi_err = SD_MMC_SPI_ERR;
sd_mmc_spi_debug("%s: Invalid Data Response Token 0x%x\n\r", __func__, resp);
return false;
}
// Check data response
switch (SPI_TOKEN_DATA_RESP_CODE(resp)) {
case SPI_TOKEN_DATA_RESP_ACCEPTED:
break;
case SPI_TOKEN_DATA_RESP_CRC_ERR:
sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE_CRC;
sd_mmc_spi_debug("%s: Write blocks, SD_MMC_SPI_ERR_CRC, resp 0x%x\n\r", __func__, resp);
return false;
case SPI_TOKEN_DATA_RESP_WRITE_ERR:
default:
sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE;
sd_mmc_spi_debug("%s: Write blocks SD_MMC_SPI_ERR_WR, resp 0x%x\n\r", __func__, resp);
return false;
}
return true;
}
bool sd_mmc_spi_start_write_blocks(const void *src, uint16_t nb_block)
{
uint32_t pos;
sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
pos = 0;
while (nb_block--) {
Assert(sd_mmc_spi_nb_block >
(sd_mmc_spi_transfert_pos / sd_mmc_spi_block_size));
sd_mmc_spi_start_write_block();
// Write block
sspi_write_packet(&((uint8_t*)src)[pos], sd_mmc_spi_block_size);
pos += sd_mmc_spi_block_size;
sd_mmc_spi_transfert_pos += sd_mmc_spi_block_size;
if (!sd_mmc_spi_stop_write_block()) {
return false;
}
// Do not check busy of last block
// but delay it to mci_wait_end_of_write_blocks()
if (nb_block) {
// Wait busy due to data programmation
if (!sd_mmc_spi_wait_busy()) {
sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE_TIMEOUT;
sd_mmc_spi_debug("%s: Write blocks timeout\n\r", __func__);
return false;
}
}
}
return true;
}
bool sd_mmc_spi_write_word(uint32_t value)
{
sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
Assert(sd_mmc_spi_nb_block >
(sd_mmc_spi_transfert_pos / sd_mmc_spi_block_size));
if (!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size)) {
// New block
sd_mmc_spi_start_write_block();
}
// Write data
value = cpu_to_le32(value);
sspi_write_packet((uint8_t*)&value, 4);
sd_mmc_spi_transfert_pos += 4;
if (!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size)) {
// End of block
if (!sd_mmc_spi_stop_write_block()) {
return false;
}
// Wait busy due to data programmation
if (!sd_mmc_spi_wait_busy()) {
sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE_TIMEOUT;
sd_mmc_spi_debug("%s: Write blocks timeout\n\r", __func__);
return false;
}
}
return sd_mmc_spi_stop_multiwrite_block();
}
/**
* \brief Executed the end of a multi blocks write transfer
*
* \return true if success, otherwise false
* with a update of \ref sd_mmc_spi_err.
*/
static bool sd_mmc_spi_stop_multiwrite_block(void)
{
uint8_t value;
if (1 == sd_mmc_spi_nb_block) {
return true; // Single block write
}
if (sd_mmc_spi_nb_block > (sd_mmc_spi_transfert_pos / sd_mmc_spi_block_size)) {
return true; // It is not the End of multi write
}
// Delay before start write block:
// Nwr timing minimum = 8 cylces
value = 0xFF;
sspi_write_packet(&value, 1);
// Send stop token
value = SPI_TOKEN_STOP_TRAN;
sspi_write_packet(&value, 1);
// Wait busy
if (!sd_mmc_spi_wait_busy()) {
sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE_TIMEOUT;
sd_mmc_spi_debug("%s: Stop write blocks timeout\n\r", __func__);
return false;
}
return true;
}
/**
* \brief Sends the correct TOKEN on the line to start a read block transfer
*
* \return true if success, otherwise false
* with a update of \ref sd_mmc_spi_err.
*/
static bool sd_mmc_spi_start_read_block(void)
{
uint32_t i;
uint8_t token;
uint16_t dummy = 0xFF;
Assert(!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size));
/* Wait for start data token:
* The read timeout is the Nac timing.
* Nac must be computed trough CSD values,
* or it is 100ms for SDHC / SDXC
* Compute the maximum timeout:
* Frequency maximum = 25MHz
* 1 byte = 8 cycles
* 100ms = 312500 x spi_read_buffer_wait() maximum
*/
token = 0;
i = 500000;
do {
if (i-- == 0) {
sd_mmc_spi_err = SD_MMC_SPI_ERR_READ_TIMEOUT;
sd_mmc_spi_debug("%s: Read blocks timeout\n\r", __func__);
return false;
}
spi_read_buffer_wait(&sd_mmc_master, &token, 1,
dummy);
if (SPI_TOKEN_DATA_ERROR_VALID(token)) {
Assert(SPI_TOKEN_DATA_ERROR_ERRORS & token);
if (token & (SPI_TOKEN_DATA_ERROR_ERROR
| SPI_TOKEN_DATA_ERROR_ECC_ERROR
| SPI_TOKEN_DATA_ERROR_CC_ERROR)) {
sd_mmc_spi_debug("%s: CRC data error token\n\r", __func__);
sd_mmc_spi_err = SD_MMC_SPI_ERR_READ_CRC;
} else {
sd_mmc_spi_debug("%s: Out of range data error token\n\r", __func__);
sd_mmc_spi_err = SD_MMC_SPI_ERR_OUT_OF_RANGE;
}
return false;
}
} while (token != SPI_TOKEN_SINGLE_MULTI_READ);
return true;
}
bool sd_mmc_spi_wait_end_of_write_blocks(void)
{
// Wait busy due to data programmation of last block writed
if (!sd_mmc_spi_wait_busy()) {
sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE_TIMEOUT;
sd_mmc_spi_debug("%s: Write blocks timeout\n\r", __func__);
return false;
}
return sd_mmc_spi_stop_multiwrite_block();
}
bool sd_mmc_spi_adtc_start(sdmmc_cmd_def_t cmd, uint32_t arg,
uint16_t block_size, uint16_t nb_block, bool access_block)
{
uint8_t dummy = 0xFF;
uint8_t cmd_token[6];
uint8_t ncr_timeout;
uint8_t r1; //! R1 response
UNUSED(access_block);
Assert(cmd & SDMMC_RESP_PRESENT); // Always a response in SPI mode
sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
// Encode SPI command
cmd_token[0] = SPI_CMD_ENCODE(SDMMC_CMD_GET_INDEX(cmd));
cmd_token[1] = arg >> 24;
cmd_token[2] = arg >> 16;
cmd_token[3] = arg >> 8;
cmd_token[4] = arg;
cmd_token[5] = sd_mmc_spi_crc7(cmd_token, 5);
// 8 cycles to respect Ncs timing
// Note: This byte does not include start bit "0",
// thus it is ignored by card.
sspi_write_packet(&dummy, 1);
// Send command
sspi_write_packet(cmd_token, sizeof(cmd_token));
// Wait for response
// Two retry will be done to manage the Ncr timing between command and reponse
// Ncr: Min. 1x8 clock cycle, Max. 8x8 clock cycles
// WORKAROUND for no compliance card (Atmel Internal ref. SD13):
r1 = 0xFF;
// Ignore first byte because Ncr min. = 8 clock cylces
sspi_read_packet(&r1, 1);
ncr_timeout = 7;
while (1) {
sspi_read_packet(&r1, 1); // 8 cycles
if ((r1 & R1_SPI_ERROR) == 0) {
// Valid R1 response
break;
}
if (--ncr_timeout == 0) {
// Here Valid R1 response received
sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lX, R1 timeout\n\r",
__func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg);
sd_mmc_spi_err = SD_MMC_SPI_ERR_RESP_TIMEOUT;
return false;
}
}
// Save R1 (Specific to SPI interface) in 32 bit response
// The R1_SPI_IDLE bit can be checked by high level
sd_mmc_spi_response_32 = r1;
// Manage error in R1
if (r1 & R1_SPI_COM_CRC) {
sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, r1 0x%02x, R1_SPI_COM_CRC\n\r",
__func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg, r1);
sd_mmc_spi_err = SD_MMC_SPI_ERR_RESP_CRC;
return false;
}
if (r1 & R1_SPI_ILLEGAL_COMMAND) {
sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, r1 0x%x, R1 ILLEGAL_COMMAND\n\r",
__func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg, r1);
sd_mmc_spi_err = SD_MMC_SPI_ERR_ILLEGAL_COMMAND;
return false;
}
if (r1 & ~R1_SPI_IDLE) {
// Other error
sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, r1 0x%x, R1 error\n\r",
__func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg, r1);
sd_mmc_spi_err = SD_MMC_SPI_ERR;
return false;
}
// Manage other responses
if (cmd & SDMMC_RESP_BUSY) {
if (!sd_mmc_spi_wait_busy()) {
sd_mmc_spi_err = SD_MMC_SPI_ERR_RESP_BUSY_TIMEOUT;
sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, Busy signal always high\n\r",
__func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg);
return false;
}
}
if (cmd & SDMMC_RESP_8) {
sd_mmc_spi_response_32 = 0;
sspi_read_packet((uint8_t*) & sd_mmc_spi_response_32, 1);
sd_mmc_spi_response_32 = le32_to_cpu(sd_mmc_spi_response_32);
}
if (cmd & SDMMC_RESP_32) {
sspi_read_packet((uint8_t*) & sd_mmc_spi_response_32, 4);
sd_mmc_spi_response_32 = be32_to_cpu(sd_mmc_spi_response_32);
}
sd_mmc_spi_block_size = block_size;
sd_mmc_spi_nb_block = nb_block;
sd_mmc_spi_transfert_pos = 0;
return true; // Command complete
}
