static int sdma_config_channel(struct sdma_channel *sdmac)
{
int ret;
sdma_disable_channel(sdmac);
sdmac->event_mask0 = 0;
sdmac->event_mask1 = 0;
sdmac->shp_addr = 0;
sdmac->per_addr = 0;
if (sdmac->event_id0) {
if (sdmac->event_id0 > 32)
return -EINVAL;
sdma_event_enable(sdmac, sdmac->event_id0);
}
switch (sdmac->peripheral_type) {
case IMX_DMATYPE_DSP:
sdma_config_ownership(sdmac, false, true, true);
break;
case IMX_DMATYPE_MEMORY:
sdma_config_ownership(sdmac, false, true, false);
break;
default:
sdma_config_ownership(sdmac, true, true, false);
break;
}
sdma_get_pc(sdmac, sdmac->peripheral_type);
if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
(sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
/* Handle multiple event channels differently */
if (sdmac->event_id1) {
sdmac->event_mask1 = 1 << (sdmac->event_id1 % 32);
if (sdmac->event_id1 > 31)
sdmac->watermark_level |= 1 << 31;
sdmac->event_mask0 = 1 << (sdmac->event_id0 % 32);
if (sdmac->event_id0 > 31)
sdmac->watermark_level |= 1 << 30;
} else {
sdmac->event_mask0 = 1 << sdmac->event_id0;
sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32);
}
/* Watermark Level */
sdmac->watermark_level |= sdmac->watermark_level;
/* Address */
sdmac->shp_addr = sdmac->per_address;
} else {
sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
}
ret = sdma_load_context(sdmac);
return ret;
}
static int sdma_config_channel(struct sdma_channel *sdmac)
{
int ret;
sdma_disable_channel(sdmac);
sdmac->event_mask0 = 0;
sdmac->event_mask1 = 0;
sdmac->shp_addr = 0;
sdmac->per_addr = 0;
if (sdmac->event_id0)
sdma_event_enable(sdmac, sdmac->event_id0);
if (sdmac->event_id1)
sdma_event_enable(sdmac, sdmac->event_id1);
switch (sdmac->peripheral_type) {
case IMX_DMATYPE_DSP:
sdma_config_ownership(sdmac, false, true, true);
break;
case IMX_DMATYPE_MEMORY:
sdma_config_ownership(sdmac, false, true, false);
break;
default:
sdma_config_ownership(sdmac, true, true, false);
break;
}
sdma_get_pc(sdmac, sdmac->peripheral_type);
if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
(sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
/* Handle multiple event channels differently */
if (sdmac->event_id1) {
if (sdmac->event_id0 > 31) {
sdmac->watermark_level |= 1 << 28;
sdmac->event_mask0 |= 0;
sdmac->event_mask1 |=
1 << ((sdmac->event_id0)%32);
} else {
sdmac->event_mask0 |=
1 << ((sdmac->event_id0)%32);
sdmac->event_mask1 |= 0;
}
if (sdmac->event_id1 > 31) {
sdmac->watermark_level |= 1 << 29;
sdmac->event_mask0 |= 0;
sdmac->event_mask1 |=
1 << ((sdmac->event_id1)%32);
} else {
sdmac->event_mask0 |=
1 << ((sdmac->event_id1)%32);
sdmac->event_mask1 |= 0;
}
sdmac->watermark_level |= (unsigned int)(3<<11);
sdmac->watermark_level |= (unsigned int)(1<<31);
sdmac->watermark_level |= (unsigned int)(2<<24);
} else {
if (sdmac->event_id0 > 31) {
sdmac->event_mask0 = 0;
sdmac->event_mask1 =
1 << ((sdmac->event_id0)%32);
} else {
sdmac->event_mask0 =
1 << ((sdmac->event_id0)%32);
sdmac->event_mask1 = 0;
}
}
/* Watermark Level */
sdmac->watermark_level |= sdmac->watermark_level;
/* Address */
switch (sdmac->direction) {
case DMA_DEV_TO_DEV:
sdmac->per_addr = sdmac->per_address;
sdmac->shp_addr = sdmac->per_address2;
break;
default:
sdmac->shp_addr = sdmac->per_address;
break;
}
} else {
sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
}
ret = sdma_load_context(sdmac);
return ret;
}
