void main(void)
{
timestamp_add_now(TS_START_ROMSTAGE);
console_init();
configure_l2ctlr();
tsadc_init();
/* vdd_log 1200mv is enough for ddr run 666Mhz */
regulate_vdd_log(1200);
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_init(get_sdram_config());
timestamp_add_now(TS_AFTER_INITRAM);
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
mmu_config_range((uintptr_t)_dram/MiB,
sdram_size_mb(), DCACHE_WRITEBACK);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
cbmem_initialize_empty();
timestamp_add_now(TS_END_ROMSTAGE);
run_ramstage();
}
static void soc_init(device_t dev)
{
ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB));
if (vboot_skip_display_init())
printk(BIOS_INFO, "Skipping display init.\n");
#if !IS_ENABLED(CONFIG_SKIP_DISPLAY_INIT_HACK)
else
rk_display_init(dev, (uintptr_t)_framebuffer,
_framebuffer_size);
#endif
}
void main(void)
{
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t start_romstage_time;
uint64_t before_dram_time;
uint64_t after_dram_time;
uint64_t base_time = timestamp_get();
start_romstage_time = timestamp_get();
#endif
console_init();
configure_l2ctlr();
tsadc_init();
/* vdd_log 1200mv is enough for ddr run 666Mhz */
regulate_vdd_log(1200);
#if CONFIG_COLLECT_TIMESTAMPS
before_dram_time = timestamp_get();
#endif
sdram_init(get_sdram_config());
#if CONFIG_COLLECT_TIMESTAMPS
after_dram_time = timestamp_get();
#endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
mmu_config_range((uintptr_t)_dram/MiB,
sdram_size_mb(), DCACHE_WRITEBACK);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(base_time);
timestamp_add(TS_START_ROMSTAGE, start_romstage_time);
timestamp_add(TS_BEFORE_INITRAM, before_dram_time);
timestamp_add(TS_AFTER_INITRAM, after_dram_time);
timestamp_add_now(TS_END_ROMSTAGE);
#endif
#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE)
void *entry = vboot2_load_ramstage();
if (entry != NULL)
stage_exit(entry);
#endif
run_ramstage();
}
/* this sucks, but for now, fb size/location are hardcoded.
* Will break if we get 2. Sigh.
* We assume it's all multiples of MiB for MMUs sake.
*/
static void soc_enable(device_t dev)
{
u32 lcdbase = fb_base_mb();
unsigned long fb_size = FB_SIZE_MB;
ram_resource(dev, 0, (uintptr_t)_dram/KiB,
(sdram_max_addressable_mb() - fb_size)*KiB -
(uintptr_t)_dram/KiB);
mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB);
u32 sdram_end_mb = sdram_size_mb() + (uintptr_t)_dram/MiB;
if (sdram_end_mb > sdram_max_addressable_mb())
ram_resource(dev, 2, sdram_max_addressable_mb()*KiB,
(sdram_end_mb - sdram_max_addressable_mb())*KiB);
}
/* this sucks, but for now, fb size/location are hardcoded.
* Will break if we get 2. Sigh.
* We assume it's all multiples of MiB for MMUs sake.
*/
static void soc_enable(device_t dev)
{
u32 lcdbase = fb_base_mb();
unsigned long fb_size = FB_SIZE_MB;
ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB,
(sdram_max_addressable_mb() - fb_size)*KiB -
CONFIG_SYS_SDRAM_BASE/KiB);
mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB);
u32 sdram_end_mb = sdram_size_mb() + CONFIG_SYS_SDRAM_BASE/MiB;
if (sdram_end_mb > sdram_max_addressable_mb())
ram_resource(dev, 2, sdram_max_addressable_mb()*KiB,
(sdram_end_mb - sdram_max_addressable_mb())*KiB);
}
void platform_romstage_main(void)
{
tsadc_init(TSHUT_POL_HIGH);
/* Init DVS to conservative values. */
init_dvs_outputs();
prepare_sdmmc();
prepare_usb();
sdram_init(get_sdram_config());
mmu_config_range((void *)0, (uintptr_t)sdram_size_mb() * MiB,
CACHED_MEM);
mmu_config_range(_dma_coherent, REGION_SIZE(dma_coherent),
UNCACHED_MEM);
}
void *cbmem_top(void)
{
return _dram + sdram_size_mb()*MiB;
}
static void soc_init(device_t dev)
{
ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB));
usb_init();
}
void *cbmem_top(void)
{
/* Make sure not to overlap with reserved ATF scratchpad */
return (void *)min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB,
4ULL * GiB);
}
static void soc_read_resources(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size_mb() * KiB);
}
void *cbmem_top(void)
{
return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB,
FU540_MAXDRAM);
}