void mtm_init_data(void)
{
int i;
info("initializing MTM data to default values");
/* reset all data to NULL, FALSE or 0 */
memset(&mtmData, 0, sizeof(mtmData));
mtmData.permanent.data.tag = MTM_TAG_PERMANENT_DATA;
/* set specification version */
mtmData.permanent.data.specMajor = 0x01;
mtmData.permanent.data.specMinor = 0x00;
/* define verified PCRs */
mtmData.permanent.data.verifiedPCRs.sizeOfSelect = TPM_NUM_PCR / 8;
for (i = 0; i < TPM_NUM_PCR / 8; i++) {
mtmData.permanent.data.verifiedPCRs.pcrSelect[i] = 0x00;
}
/* map MTM counters to TPM counters */
set_counter(MTM_COUNTER_SELECT_BOOTSTRAP, "MTM1");
set_counter(MTM_COUNTER_SELECT_RIMPROTECT, "MTM2");
set_counter(MTM_COUNTER_SELECT_STORAGEPROTECT, "MTM3");
/* the field integrityCheckRootData is filled when the first verification key is loaded */
memset(mtmData.permanent.data.integrityCheckRootData, 0xff,
sizeof(mtmData.permanent.data.integrityCheckRootData));
/* set internal verification key */
memcpy(mtmData.permanent.data.internalVerificationKey,
"\x77\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x77", sizeof(TPM_SECRET));
/* init flags */
mtmData.stany.flags.tag = MTM_TAG_STANY_FLAGS;
mtmData.stany.flags.loadVerificationRootKeyEnabled = TRUE;
}
void gamedata::set_life(word l)
{
if(l <= 0) l = 0;
set_counter(l, 0);
return;
}
void MsgItem::MergeFrom(const MsgItem& from) {
GOOGLE_CHECK_NE(&from, this);
item_.MergeFrom(from.item_);
if (from._has_bits_[0 / 32] & (0xffu << (0 % 32))) {
if (from._has_bit(0)) {
set_sku(from.sku());
}
if (from._has_bit(1)) {
set_position(from.position());
}
if (from._has_bit(3)) {
set_sequence(from.sequence());
}
if (from._has_bit(4)) {
set_counter(from.counter());
}
if (from._has_bit(5)) {
set_quantity(from.quantity());
}
if (from._has_bit(6)) {
set_timeleft(from.timeleft());
}
}
mutable_unknown_fields()->MergeFrom(from.unknown_fields());
}
static struct recording generate_recording(u8 counter_start,
uint8_t set_counter(uint8_t data, uint8_t counter),
u8 counter_modulo,
size_t size)
{
size_t i;
u8* samples;
u8 counter;
struct recording recording = {NULL, 0};
samples = malloc(size);
if (NULL == samples) {
return recording;
}
counter = counter_start;
for (i = 0; i < size; i++) {
samples[i] = set_counter(samples[i], counter);
counter++;
counter %= counter_modulo;
}
recording.samples = samples;
recording.size = size;
return recording;
}
/*
* Test whether writefd is not set by select when counter value is at
* (UINT64_MAX - 1).
*/
static void writefd_not_set_test(int fd)
{
int ret;
fd_set writefds;
struct timeval timeout = { 0, 0 };
FD_ZERO(&writefds);
FD_SET(fd, &writefds);
ret = set_counter(fd, UINT64_MAX - 1);
if (ret == -1) {
tst_resm(TBROK, "error setting counter value to UINT64_MAX-1");
return;
}
ret = select(fd + 1, NULL, &writefds, NULL, &timeout);
if (ret == -1) {
/* EINTR cannot occur, since we don't block. */
tst_resm(TBROK | TERRNO, "select: error getting fd status");
return;
}
if (!FD_ISSET(fd, &writefds))
tst_resm(TPASS, "fd is not set in writefds");
else
tst_resm(TFAIL, "fd is set in writefds");
}
/*
* Test whether readfd is set by select when counter value is
* non-zero.
*/
static void readfd_set_test(int fd)
{
int ret;
fd_set readfds;
struct timeval timeout = { 0, 0 };
uint64_t non_zero = 10;
FD_ZERO(&readfds);
FD_SET(fd, &readfds);
ret = set_counter(fd, non_zero);
if (ret == -1) {
tst_resm(TBROK, "error setting counter value to %" PRIu64,
non_zero);
return;
}
ret = select(fd + 1, &readfds, NULL, NULL, &timeout);
if (ret == -1) {
/* EINTR cannot occur, since we don't block. */
tst_resm(TBROK | TERRNO, "select() failed");
return;
}
if (FD_ISSET(fd, &readfds))
tst_resm(TPASS, "fd is set in readfds");
else
tst_resm(TFAIL, "fd is not set in readfds");
}
static long dma_r_ioctl(struct file * file, unsigned int cmd, unsigned long value) {
char * tmp;
struct dma_page_pointer * tmppnt;
int ilocal;
unsigned long w4,adr,tmpval;
char val;
switch(cmd) {
case NUDAQ_2_START_DMA: case NUDAQ_4_START_DMA:
if (!dma_main_pointer){ nu2err=E_NU_nopointer; return -EINVAL; }
if (dma_should_run) { nu2err=E_NU_already_running; return -EINVAL;}
start_dma_engine(); /* 160503 */
break;
case NUDAQ_2_STOP_DMA: case NUDAQ_4_STOP_DMA:
if (!dma_main_pointer){ nu2err=E_NU_nopointer; return -EINVAL; }
if (!dma_should_run) { nu2err=E_NU_not_running; return -EINVAL;}
shutoff_dma_engine();
break;
case NUDAQ_2_READ_ERR: case NUDAQ_4_READ_ERR:
return nu2err; break;
case NUDAQ_2_BYTES_READ: case NUDAQ_4_BYTES_SENT:
return get_bytes_transfered();break;
case NUDAQ_2_OUTWORD:
outl(value,iocard_base+0x14);break;
case NUDAQ_4_INWORD:
return inl(iocard_base+0x10);break;
case NUDAQ_2_READBACK:
return inl(iocard_base+0x14);break;
case NUDAQ_2_DITIMERS: /* set internal timers and corresp. cascade mode */
set_counter(0, value & 0x0ffff);
tmpval=inl(iocard_base+0x1c) & ~0x0400; /* T0_T2 bit isolation */
if (value & 0xffff0000) {
set_counter(2,(value>>16));
tmpval |= 0x0400; /* set T0_T2 cascade enable bit */
};
outl(tmpval,iocard_base+0x1c);
break;
case NUDAQ_4_DITIMERS: /* set internal timers and corresp. cascade mode */
set_counter(1, value & 0x0ffff);
tmpval=inl(iocard_base+0x1c) & ~0x0800; /* T1_T2 bit isolation */
if (value & 0xffff0000) {
set_counter(2,(value>>16));
tmpval |= 0x0800; /* set T1_T2 cascade enable bit */
};
/*
* stress_timer
* stress timers
*/
static int stress_timer(const args_t *args)
{
struct sigevent sev;
struct itimerspec timer;
sigset_t mask;
uint64_t timer_freq = DEFAULT_TIMER_FREQ;
(void)sigemptyset(&mask);
(void)sigaddset(&mask, SIGINT);
(void)sigprocmask(SIG_SETMASK, &mask, NULL);
max_ops = args->max_ops;
start = time_now();
if (!get_setting("timer-freq", &timer_freq)) {
if (g_opt_flags & OPT_FLAGS_MAXIMIZE)
timer_freq = MAX_TIMER_FREQ;
if (g_opt_flags & OPT_FLAGS_MINIMIZE)
timer_freq = MIN_TIMER_FREQ;
}
rate_ns = timer_freq ? 1000000000.0 / timer_freq : 1000000000.0;
if (stress_sighandler(args->name, SIGRTMIN, stress_timer_handler, NULL) < 0)
return EXIT_FAILURE;
sev.sigev_notify = SIGEV_SIGNAL;
sev.sigev_signo = SIGRTMIN;
sev.sigev_value.sival_ptr = &timerid;
if (timer_create(CLOCK_REALTIME, &sev, &timerid) < 0) {
pr_fail_err("timer_create");
return EXIT_FAILURE;
}
stress_timer_set(&timer);
if (timer_settime(timerid, 0, &timer, NULL) < 0) {
pr_fail_err("timer_settime");
return EXIT_FAILURE;
}
do {
struct timespec req;
req.tv_sec = 0;
req.tv_nsec = 10000000;
(void)nanosleep(&req, NULL);
set_counter(args, timer_counter);
} while (keep_stressing());
if (timer_delete(timerid) < 0) {
pr_fail_err("timer_delete");
return EXIT_FAILURE;
}
pr_dbg("%s: %" PRIu64 " timer overruns (instance %" PRIu32 ")\n",
args->name, overruns, args->instance);
return EXIT_SUCCESS;
}
/*
* Test whether writing to counter works.
*/
static void write_test(int fd)
{
int ret;
uint64_t val;
val = 12;
ret = set_counter(fd, val);
if (ret == -1) {
tst_resm(TBROK, "error setting counter value to %" PRIu64, val);
return;
}
read_test(fd, val);
}
/*
* Test whether counter overflow is detected and handled correctly.
*
* It is not possible to directly overflow the counter using the
* write() syscall. Overflows occur when the counter is incremented
* from kernel space, in an irq context, when it is not possible to
* block the calling thread of execution.
*
* The AIO subsystem internally uses eventfd mechanism for
* notification of completion of read or write requests. In this test
* we trigger a counter overflow, by setting the counter value to the
* max possible value initially. When the AIO subsystem notifies
* through the eventfd counter, the counter overflows.
*
* NOTE: If the the counter starts from an initial value of 0, it will
* take decades for an overflow to occur. But since we set the initial
* value to the max possible counter value, we are able to cause it to
* overflow with a single increment.
*
* When the counter overflows, the following are tested
* 1. Check whether POLLERR event occurs in poll() for the eventfd.
* 2. Check whether readfd_set/writefd_set is set in select() for the
eventfd.
* 3. The counter value is UINT64_MAX.
*/
static int trigger_eventfd_overflow(int evfd, int *fd, io_context_t * ctx)
{
int ret;
struct iocb iocb;
struct iocb *iocbap[1];
static char buf[4 * 1024];
*ctx = 0;
ret = io_setup(16, ctx);
if (ret < 0) {
errno = -ret;
tst_resm(TINFO | TERRNO, "io_setup error");
return -1;
}
*fd = open("testfile", O_RDWR | O_CREAT, 0644);
if (*fd == -1) {
tst_resm(TINFO | TERRNO, "open(testfile) failed");
goto err_io_destroy;
}
ret = set_counter(evfd, UINT64_MAX - 1);
if (ret == -1) {
tst_resm(TINFO, "error setting counter to UINT64_MAX-1");
goto err_close_file;
}
io_prep_pwrite(&iocb, *fd, buf, sizeof(buf), 0);
io_set_eventfd(&iocb, evfd);
iocbap[0] = &iocb;
ret = io_submit(*ctx, 1, iocbap);
if (ret < 0) {
errno = -ret;
tst_resm(TINFO | TERRNO, "error submitting iocb");
goto err_close_file;
}
return 0;
err_close_file:
close(*fd);
err_io_destroy:
io_destroy(*ctx);
return -1;
}
/*
* Test whether write returns with error EAGAIN when counter is at
* (UINT64_MAX - 1).
*/
static void write_eagain_test(int fd)
{
int ret;
uint64_t val;
ret = set_counter(fd, UINT64_MAX - 1);
if (ret == -1) {
tst_resm(TBROK, "error setting counter value to UINT64_MAX-1");
return;
}
val = 1;
ret = write(fd, &val, sizeof(val));
if (ret == -1) {
if (errno == EAGAIN)
tst_resm(TPASS, "write failed with EAGAIN as expected");
else
tst_resm(TFAIL, "write failed (wanted EAGAIN)");
} else
tst_resm(TFAIL, "write returned with %d", ret);
}
void gamedata::set_rupies(word r)
{
set_counter(r, 1);
return;
}
static rc_t spotgroup_enter_values( spotgrp * spotgroup,
uint64_t *entries,
const uint8_t quality,
const uint8_t dimer_code,
const uint8_t gc_content,
const uint8_t hp_run,
const uint8_t max_quality,
const uint8_t n_read,
const uint32_t cycle,
const uint8_t rd_case,
const uint64_t row_id )
{
rc_t rc = 0;
uint8_t q = quality;
uint8_t d = dimer_code;
uint8_t g = gc_content;
uint8_t h = hp_run;
uint8_t m = max_quality;
uint8_t n = n_read;
#ifdef USE_JUDY
bool mismatch;
#else
counter_vector * cv;
#endif
if ( q >= N_QUAL_VALUES ) q = ( N_QUAL_VALUES - 1 );
if ( d >= N_DIMER_VALUES ) d = ( N_DIMER_VALUES - 1 );
if ( g >= N_GC_VALUES ) g = ( N_GC_VALUES - 1 );
if ( h >= N_HP_VALUES ) h = ( N_HP_VALUES - 1 );
if ( m >= N_MAX_QUAL_VALUES ) m = ( N_MAX_QUAL_VALUES - 1 );
if ( n >= N_READS ) n = ( N_READS - 1 );
#ifdef USE_JUDY
mismatch = false;
switch( rd_case )
{
case CASE_MISMATCH : mismatch = true; /* no break intented! */
case CASE_MATCH : if ( set_counter( spotgroup->v, cycle, m, n, d, g, h, q, mismatch ) )
{
(*entries)++;
}
break;
}
#else
cv = &( spotgroup->cnv[ m ][ n ][ d ][ g ][ h ][ q ] );
if ( cv->v == NULL )
{
/* the counter-block was not used before at all */
cv->n_counters = ( ( cycle / COUNTER_BLOCK_SIZE ) + 1 ) * COUNTER_BLOCK_SIZE;
cv->v = calloc( cv->n_counters, sizeof cv->v[0] );
if ( cv->v == NULL )
{
rc = RC( rcApp, rcNoTarg, rcConstructing, rcMemory, rcExhausted );
PLOGERR( klogInt, ( klogInt, rc,
"calloc() failed at row#$(row_nr) cycle#$(cycle)",
"row_nr=%lu,cycle=%u", row_id, cycle ) );
}
}
else
{
if ( cycle >= cv->n_counters )
{
/* the counter-block has to be extended */
void * tmp;
uint32_t org_len = cv->n_counters;
cv->n_counters = ( ( cycle / COUNTER_BLOCK_SIZE ) + 1 ) * COUNTER_BLOCK_SIZE;
/* prevent from leaking memory by capturing the new pointer in temp. var. */
tmp = realloc( cv->v, cv->n_counters * ( sizeof cv->v[0] ) );
if ( tmp == NULL )
{
rc = RC( rcApp, rcNoTarg, rcConstructing, rcMemory, rcExhausted );
PLOGERR( klogInt, ( klogInt, rc,
"realloc() failed at row#$(row_nr) cycle#$(cycle)",
"row_nr=%lu,cycle=%u", row_id, cycle ) );
}
else
{
/* the added part has to be set to zero */
counter * to_zero_out = tmp;
to_zero_out += org_len;
memset( to_zero_out, 0, ( cv->n_counters - org_len ) * ( sizeof *to_zero_out ) );
cv->v = tmp;
}
}
}
assert( cycle < cv->n_counters );
if ( rc == 0 )
{
counter * cnt = &( cv->v[ cycle ] );
switch( rd_case )
{
case CASE_MISMATCH : cnt->mismatches++; /* no break intented! */
case CASE_MATCH : if ( cnt->count == 0 )
{
(*entries)++;
}
cnt->count++;
break;
}
}
#endif
return rc;
}
static int dma_r_ioctl(struct inode * inode, struct file * file, unsigned int cmd, unsigned long value) {
char * tmp;
unsigned long w4,adr,tmpval;
char val;
switch(cmd) {
case NUDAQ_2_START_DMA:
if (!dma_main_pointer){ nu2err=E_NU2_nopointer; return -EINVAL; }
if (dma_should_run) { nu2err=E_NU2_already_running; return -EINVAL;}
start_dma_engine();
break;
case NUDAQ_2_STOP_DMA:
if (!dma_main_pointer){ nu2err=E_NU2_nopointer; return -EINVAL; }
if (!dma_should_run) { nu2err=E_NU2_not_running; return -EINVAL;}
shutoff_dma_engine();
break;
case NUDAQ_2_READ_ERR:
return nu2err; break;
case NUDAQ_2_BYTES_READ:
return get_bytes_transfered();break;
case NUDAQ_2_OUTWORD:
outl(value,iocard_base+0x14);break;
case NUDAQ_2_READBACK:
return inl(iocard_base+0x14);break;
case NUDAQ_2_DITIMERS: /* set internal timers and corresp. cascade mode */
set_counter(0, value & 0x0ffff);
tmpval=inl(iocard_base+0x1c) & ~0x0400; /* T0_T2 bit isolation */
if (value & 0xffff0000) {
set_counter(2,(value>>16));
tmpval |= 0x0400; /* set T0_T2 cascade enable bit */
};
outl(tmpval,iocard_base+0x1c);
break;
case NUDAQ_2_INMODE:
return setinmode(value);
break;
/* for debugging: */
case 0x2001:
/* write to buffer adr mit offset, return kernel adr */
tmp=dma_main_pointer->buffer;
tmp[(value>>8)&0xff]=(value & 0xff);
return (unsigned int)tmp[(value>>8)&0xff];
break;
case 0x2002:
/* read buffer mot offset */
tmp=dma_main_pointer->buffer;
val=tmp[(value>>8)&0xff];
return (unsigned int)val;
break;
case 0x2003:
return (int)value;
break;
case 0x2004:
/* set adr register */
adr2 = value;
return 0;
break;
case 0x2005:
/* re-read adr register */
return (int) adr2;
break;
case 0x2006:case 0x2008:
/* set register in adr space 1 directly */
w4=value;adr=(adr2 & 0x3c)+(cmd==0x2006?iocard_base:dma_engine_base);
outl(w4,adr);
break;
case 0x2007:case 0x2009:
/* read register in adr space 1 directly */
adr=(adr2 & 0x3c)+(cmd==0x2007?iocard_base:dma_engine_base);
return (int)inl(adr);
break;
case 0x200a:
/* read bus master control status reg */
return (int) inl(dma_engine_base+0x3c);
break;
case 0x200b:
/* read interrupt control register */
return (int) inl(dma_engine_base+0x38);
break;
case 0x200c:
/* read saved value diovalsave */
return (int)diovalsave;
break;
case 0x200d:
/* read MWTC register */
return (int)inl(dma_engine_base+0x28);
break;
default:
return -EINVAL;
};
void inc() { set_counter(get_counter() + 1); }
void gamedata::set_magic(word m)
{
set_counter(m, 4);
return;
}
void gamedata::set_sbombs(word k)
{
set_counter(k, 6);
return;
}
void gamedata::set_keys(word k)
{
set_counter(k, 5);
return;
}
void gamedata::set_arrows(word a)
{
set_counter(a, 3);
}
void dec() { set_counter(get_counter() - 1); }
