static void gpio_pin_config(struct device *dev, u32_t pin, int flags)
{
const struct gpio_sch_config *info = dev->config->config_info;
struct gpio_sch_data *gpio = dev->driver_data;
u8_t active_high = 0U;
u8_t active_low = 0U;
z_set_bit_gen(info->regs, pin, 1);
z_set_bit_gio(info->regs, pin, !(flags & GPIO_DIR_MASK));
if (flags & GPIO_INT) {
if (flags & GPIO_INT_DOUBLE_EDGE) {
active_high = 1U;
active_low = 1U;
} else if (flags & GPIO_INT_ACTIVE_HIGH) {
active_high = 1U;
} else {
active_low = 1U;
}
LOG_DBG("Setting up pin %d to active_high %d and "
"active_low %d", pin, active_high, active_low);
}
/* We store the gtpe/gtne settings. These will be used once
* we enable the callback for the pin, or the whole port
*/
set_data_reg(&gpio->int_regs.gtpe, pin, active_high);
set_data_reg(&gpio->int_regs.gtne, pin, active_low);
}
T_BOOL sd_rx_data_cpu(T_pSD_DEVICE drv_card, T_U8 buf[], T_U32 len)
{
T_U32 status;
T_U32 buf_tmp;
T_U32 i;
T_U32 offset, size;
REG32(s_SdReg_Base + oSD_DMA_MODE) = 0;
set_data_reg(len, drv_card->ulDataBlockLen, drv_card->enmBusMode, 1);
offset = 0;
size = len;
while(1)
{
status = REG32(s_SdReg_Base + oSD_INT_STA);
if ((status & DATA_BUF_FULL))
{
buf_tmp = REG32(s_SdReg_Base + oSD_CPU_MODE);
for (i = 0; i < 4; i++)
{
buf[offset + i] = (T_U8)((buf_tmp >> (i * 8)) & 0xff);
}
offset += 4;
size -= 4;
}
if ((size > 0) && (size < 4) && (status & DATA_END))
{
buf_tmp = REG32(s_SdReg_Base + oSD_CPU_MODE);
for ( i = 0; i < size; i++)
{
buf[offset + i] = (T_U8)((buf_tmp >> (i * 8)) & 0xff);
}
size = 0;
}
//fetch/excecute cycle.
int fetchEx(void) {
interruptCPU(); //Check for interrupts.
IR = getWord(PC); // Instruction Placed in the Instruction Register.
char buf[50];
sprintf(buf, "PC: 0%o \n", PC);
debug_print(buf);
//sprintf(buf, "INSTR: 0%o\n", IR);
//debug_print(buf);
//debug_print("R0 val:");
//toBin(reg[0]);
//debug_print("\n");
PC+=2; // Program counter is incremented by 2 to point to the next Word location.
//Instruction Decoding:
//halt
if (IR == 0) {
return 1;
}
//RESET
else if (IR == 000005) {
//sleep
debug_print("RESET\n");
struct timespec req, rem;
req.tv_sec = 0;
req.tv_nsec = 70000000; //70 ms
//DATA = r0
set_data_reg(reg[0]);
updateregsdisplay();
nanosleep(&req, &rem);
}
// Branch on microtest (BUT).
//Check to see if it is a double operand instruction.
else if ((IR & 070000) != 0) {
uint16_t op = IR >> 12;
uint16_t dst = IR & 077;
uint16_t src = (IR & SOURCE) >> 6;
int16_t srcVal;
int8_t srcValByte;
int16_t result;
int8_t resultByte;
int16_t oldVal;
int16_t dstVal;
int8_t dstValByte;
uint8_t r = (IR & 0000700) >> 6;
uint16_t tmpand;
switch(IR & 0177000) {
case 070000: // MUL
tmpand = (IR & 0177000);
sprintf(buf, "\nIR & 0177000: %o", tmpand);
debug_print(buf);
debug_print("MUL\n");
srcVal = getMem(dst, WORD);
uint8_t r = (IR & 0000700) >> 6;
int32_t result = reg[r] * srcVal;
psw.V = 0;
psw.N = 0;
psw.C = 0;
if(result > 0177777 || result < ~0177777)
psw.C = 1;
if(result < 0)
psw.N = 1;
if (r % 2 == 0) {
reg[r] = (result >> 16) & 0177777;
reg[r + 1] = result & 0177777;
debug_print("MUL % 2\n");
sprintf(buf, "r in octal: %o .\n", reg[r]);
debug_print(buf);
sprintf(buf, "r+1 in octal: %o .\n", reg[r+1]);
debug_print(buf);
}
else {
/**
* @brief SD read or write data use l2 dma
*
* start l2 dma
* @author Huang Xin
* @date 2010-07-14
* @param drv_card[in] the handle of sd card
* @param ram_addr[in] the ram address used by dma
* @param size[in] transfer bytes
* @param dir[in] transfer direction
* @return T_BOOL
* @retval AK_TRUE: transfer successfully
* @retval AK_FALSE: transfer failed
*/
T_BOOL sd_trans_data_dma(T_pSD_DEVICE drv_card, T_U32 ram_addr, T_U32 size, T_U8 dir)
{
T_U32 tmp;
T_U32 pBuff_addr;
T_U32 pBuff_len;
T_BOOL ret;
//alloc L2 buffer
ret = l2_init_device_buf(s_L2Select);
if(AK_FALSE == ret)
{
return AK_FALSE;
}
ret = get_device_buf_info(s_L2Select, &pBuff_addr, &pBuff_len, &tmp);
if(AK_FALSE == ret)
{
goto EXIT;
}
sd_cfg_buf(L2_CPU_MODE, pBuff_addr, pBuff_len);
//set data reg
set_data_reg(size, drv_card->ulDataBlockLen, drv_card->enmBusMode, dir);
//set l2 trans dir
if (SD_DATA_CTL_TO_HOST == dir)
{
ret = l2_trans_data_cpu(ram_addr, s_L2Select, size, 0);
}
else
{
ret = l2_trans_data_cpu(s_L2Select, ram_addr, size, 0);
}
if(AK_FALSE == ret)
{
drv_print("sd dma fail", dir, AK_TRUE);
goto EXIT;
}
while (1)
{
tmp = REG32(s_SdReg_Base + oSD_INT_STA);
if ((tmp & DATA_TIME_OUT) || (tmp & DATA_CRC_FAIL))
{
drv_print("sd data error", tmp, AK_TRUE);
ret = AK_FALSE;
break;
}
if (SD_DATA_CTL_TO_HOST == dir && !(tmp & RX_ACTIVE))
{
break;
}
else if (SD_DATA_CTL_TO_CARD == dir && !(tmp & TX_ACTIVE))
{
break;
}
}
EXIT:
l2_release_device_buf(s_L2Select);
return ret;
}
