void __init arch_init_irq(void)
{
int i;
clear_c0_status(0xff04); /* clear ERL */
set_c0_status(0x0400); /* set IP2 */
/* Set up MIPS CPU irq */
mips_cpu_irq_init();
/* Set up INTC irq */
intc_base = ioremap(INTC_IOBASE, 0xfff);
writel(0xffffffff, intc_base + IMSR_OFF);
writel(0xffffffff, intc_base + PART_OFF + IMSR_OFF);
for (i = IRQ_INTC_BASE; i < IRQ_INTC_BASE + INTC_NR_IRQS; i++) {
irq_set_chip_data(i, (void *)(i - IRQ_INTC_BASE));
irq_set_chip_and_handler(i, &jzintc_chip, handle_level_irq);
}
for (i = IRQ_OST_BASE; i < IRQ_OST_BASE + OST_NR_IRQS; i++) {
irq_set_chip_data(i, (void *)(i - IRQ_OST_BASE));
irq_set_chip_and_handler(i, &ost_irq_type, handle_level_irq);
}
#ifdef CONFIG_SMP
init_intc_affinity();
set_intc_cpu(26,0);
set_intc_cpu(27,1);
#endif
/* enable cpu interrupt mask */
set_c0_status(IE_IRQ0 | IE_IRQ1);
#ifdef CONFIG_SMP
setup_ipi();
#endif
return;
}
void jz_set_cpu_affinity(unsigned long irq,int cpu) {
set_intc_cpu(irq - IRQ_INTC_BASE,cpu);
}
