int misc_init_r(void) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; __maybe_unused ccsr_gur_t *gur; u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw3; gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_SRIO1 if (is_serdes_configured(SRIO1)) { set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_RIO_1); } else { printf (" SRIO1: disabled\n"); } #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ #endif #ifdef CONFIG_SRIO2 if (is_serdes_configured(SRIO2)) { set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_RIO_2); } else { printf (" SRIO2: disabled\n"); } #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ #endif /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. */ sw3 = in_8(&PIXIS_SW(3)); actual[0] = (sw3 & 0x40) ? SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; actual[1] = (sw3 & 0x20) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; actual[2] = (sw3 & 0x10) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; for (i = 0; i < NUM_SRDS_BANKS; i++) { u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) { printf("Warning: SERDES bank %u expects reference clock" " %sMHz, but actual is %sMHz\n", i + 1, serdes_clock_to_string(expected), serdes_clock_to_string(actual[i])); } } return 0; }
void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int first_free_busno = 0; #ifdef CONFIG_PCI1 struct fsl_pci_info pci_info; u32 devdisr, pordevsr, io_sel; u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); porpllsr = in_be32(&gur->porpllsr); io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); pci_speed = 66666000; pci_32 = 1; pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { SET_STD_PCI_INFO(pci_info, 1); set_next_law(pci_info.mem_phys, law_size_bits(pci_info.mem_size), pci_info.law); set_next_law(pci_info.io_phys, law_size_bits(pci_info.io_size), pci_info.law); pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", pci_info.regs); #ifndef CONFIG_PCI_PNP pci1_hose.config_table = pci_mpc8568mds_config_table; #endif first_free_busno = fsl_pci_init_port(&pci_info, &pci1_hose, first_free_busno); } else { printf("PCI: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif fsl_pcie_init_board(first_free_busno); }
/* Fixed sdram init -- doesn't use serial presence detect. */ void sdram_init(void) { ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); __raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2); __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); __raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl); __raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl); __raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1); __raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2); /* Set, but do not enable the memory */ __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg); asm volatile("sync;isync"); udelay(500); /* Let the controller go */ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); }
/* Fixed sdram init -- doesn't use serial presence detect. */ phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2); out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2); out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); #endif return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024ul; }
static void sdram_init(void) { struct ccsr_ddr __iomem *ddr = (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; #if CONFIG_DDR_CLK_FREQ == 100000000 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2); __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); __raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4); __raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5); __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); #elif CONFIG_DDR_CLK_FREQ == 133000000 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); __raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); __raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2); __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); __raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3); __raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0); __raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1); __raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2); __raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode); __raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2); __raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval); __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl); __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl); __raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4); __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5); __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); #else puts("Not a valid DDR Freq Found! Please Reset\n"); #endif asm volatile("sync;isync"); udelay(500); /* Let the controller go */ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); }
void pci_init_board(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; struct fsl_pci_info pci_info; u32 devdisr; int first_free_busno; int pci_agent; devdisr = in_be32(&gur->devdisr); first_free_busno = fsl_pcie_init_board(0); #ifdef CONFIG_PCI1 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) { SET_STD_PCI_INFO(pci_info, 1); set_next_law(pci_info.mem_phys, law_size_bits(pci_info.mem_size), pci_info.law); set_next_law(pci_info.io_phys, law_size_bits(pci_info.io_size), pci_info.law); pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); printf("PCI: connected to PCI slots as %s" \ " (base address %lx)\n", pci_agent ? "Agent" : "Host", pci_info.regs); #ifndef CONFIG_PCI_PNP pci1_hose.config_table = pci_mpc86xxcts_config_table; #endif first_free_busno = fsl_pci_init_port(&pci_info, &pci1_hose, first_free_busno); } else { printf("PCI: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */ #endif fsl_pcie_init_board(first_free_busno); }
void sdram_init(void) { ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE); out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); if (ddr_freq_mhz < 700) { out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667); out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667); out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667); out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667); out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667); out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667); out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667); out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667); out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CONTROL_667); } else { out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800); out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800); out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800); out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800); out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800); out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800); out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800); out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800); out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CONTROL_800); } out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL); /* mimic 500us delay, with busy isync() loop */ udelay(100); /* Let the controller go */ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); }
void init_laws(void) { int i; gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, law_table[i].trgt_id); else set_law(law_table[i].index, law_table[i].addr, law_table[i].size, law_table[i].trgt_id); } return ; }
void init_laws(void) { int i; #if FSL_HW_NUM_LAWS < 32 gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); #elif FSL_HW_NUM_LAWS == 32 gd->used_laws = 0; #else #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes #endif /* * Any LAWs that were set up before we booted assume they are meant to * be around and mark them used. */ for (i = 0; i < FSL_HW_NUM_LAWS; i++) { u32 lawar = in_be32(LAWAR_ADDR(i)); if (lawar & LAW_EN) gd->used_laws |= (1 << i); } #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) /* * in NAND boot we've already parsed the law_table and setup those LAWs * so don't do it again. */ return; #endif for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, law_table[i].trgt_id); else set_law(law_table[i].index, law_table[i].addr, law_table[i].size, law_table[i].trgt_id); } return ; }
void init_laws(void) { int i; #if FSL_HW_NUM_LAWS < 32 gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); #elif FSL_HW_NUM_LAWS == 32 gd->used_laws = 0; #else #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes #endif for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, law_table[i].trgt_id); else set_law(law_table[i].index, law_table[i].addr, law_table[i].size, law_table[i].trgt_id); } return ; }
void pci_init_board(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct fsl_pci_info pci_info[4]; u32 devdisr, pordevsr, io_sel, sdrs2_io_sel; u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; int first_free_busno = 0; int num = 0; int pcie_ep, pcie_configured; devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); porpllsr = in_be32(&gur->porpllsr); io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; sdrs2_io_sel = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x\n", devdisr, sdrs2_io_sel, io_sel); if (sdrs2_io_sel == 7) printf("Serdes2 disalbed\n"); else if (sdrs2_io_sel == 4) { printf("eTSEC1 is in sgmii mode.\n"); printf("eTSEC3 is in sgmii mode.\n"); } else if (sdrs2_io_sel == 6) printf("eTSEC1 is in sgmii mode.\n"); puts("\n"); #ifdef CONFIG_PCIE3 pcie_configured = is_serdes_configured(PCIE3); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3); set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3); SET_STD_PCIE_INFO(pci_info[num], 3); pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); printf("PCIE3: connected to Slot3 as %s (base address %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie3_hose, first_free_busno); } else { printf("PCIE3: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ #endif #ifdef CONFIG_PCIE1 pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1); set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1); SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf("PCIE1: connected to Slot1 as %s (base address %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { printf("PCIE1: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif #ifdef CONFIG_PCIE2 pcie_configured = is_serdes_configured(PCIE2); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2); set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2); SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf("PCIE2: connected to Slot 2 as %s (base address %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); } else { printf("PCIE2: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ #endif #ifdef CONFIG_PCI1 pci_speed = 66666000; pci_32 = 1; pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI); set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI); SET_STD_PCI_INFO(pci_info[num], 1); pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pci1_hose, first_free_busno); } else { printf("PCI: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif }
void init_laws(void) { int i; #if FSL_HW_NUM_LAWS < 32 gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); #elif FSL_HW_NUM_LAWS == 32 gd->used_laws = 0; #else #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes #endif /* * Any LAWs that were set up before we booted assume they are meant to * be around and mark them used. */ for (i = 0; i < FSL_HW_NUM_LAWS; i++) { u32 lawar = in_be32(LAWAR_ADDR(i)); if (lawar & LAW_EN) gd->used_laws |= (1 << i); } #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) /* * in NAND boot we've already parsed the law_table and setup those LAWs * so don't do it again. */ return; #endif for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, law_table[i].trgt_id); else set_law(law_table[i].index, law_table[i].addr, law_table[i].size, law_table[i].trgt_id); } #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* check RCW to get which port is used for boot */ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; u32 bootloc = in_be32(&gur->rcwsr[6]); /* * in SRIO or PCIE boot we need to set specail LAWs for * SRIO or PCIE interfaces. */ switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) { case 0x0: /* boot from PCIE1 */ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1); set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1); break; case 0x1: /* boot from PCIE2 */ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2); set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2); break; case 0x2: /* boot from PCIE3 */ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_3); set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_3); break; case 0x8: /* boot from SRIO1 */ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_1); set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_1); break; case 0x9: /* boot from SRIO2 */ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_2); set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_2); break; default: break; } #endif return ; }
void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct fsl_pci_info pci_info; u32 devdisr, pordevsr, io_sel; u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; int first_free_busno = 0; char buf[32]; devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); porpllsr = in_be32(&gur->porpllsr); io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); #ifdef CONFIG_PCI1 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { SET_STD_PCI_INFO(pci_info, 1); set_next_law(pci_info.mem_phys, law_size_bits(pci_info.mem_size), pci_info.law); set_next_law(pci_info.io_phys, law_size_bits(pci_info.io_size), pci_info.law); pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, strmhz(buf, pci_speed), pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", pci_info.regs); pci1_hose.config_table = pci_mpc85xxcds_config_table; first_free_busno = fsl_pci_init_port(&pci_info, &pci1_hose, first_free_busno); #ifdef CONFIG_PCIX_CHECK if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) { /* PCI-X init */ if (CONFIG_SYS_CLK_FREQ < 66000000) printf("PCI-X will only work at 66 MHz\n"); reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); } #endif } else { printf("PCI1: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif #ifdef CONFIG_PCI2 { uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ if (pci_dual) { printf("PCI2: 32 bit, 66 MHz, %s\n", pci2_clk_sel ? "sync" : "async"); } else { printf("PCI2: disabled\n"); } } #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ #endif /* CONFIG_PCI2 */ fsl_pcie_init_board(first_free_busno); }